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Experimental measurement of a novel power gating structure with intermediate power saving mode
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Authors:
Suhwan Kim
Seoul National Univestiy, Seoul, Korea
Stephen V. Kosonocky
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Daniel R. Knebel
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Kevin Stawiasz
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
2004 Article
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Published in:
· Proceeding
ISLPED '04
Proceedings of the 2004 international symposium on Low power electronics and design
Pages 20 - 25
ACM
New York, NY
, USA
©2004
table of contents
ISBN:1-58113-929-2
doi>
10.1145/1013235.1013246
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advanced technologies
clock gating
design
ground bounce
inductive noise
microprocessors and microcomputers
power gating
reliability
system-on-a-chip design
wake-up latency
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