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Memory accesses management during high level synthesis
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Authors:
Gwenolé Corre
University of South Brittany, LORIENT cedex, France
Eric Senn
University of South Brittany, LORIENT cedex, France
Pierre Bomel
University of South Brittany, LORIENT cedex, France
Nathalie Julien
University of South Brittany, LORIENT cedex, France
Eric Martin
University of South Brittany, LORIENT cedex, France
2004 Article
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Published in:
· Proceeding
CODES+ISSS '04
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Pages 42-47
ACM
New York, NY
, USA
©2004
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ISBN:1-58113-937-3
doi>
10.1145/1016720.1016733
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Tags:
algorithms
behavioral synthesis
design
experimentation
memory aware
register-transfer-level implementation
theory
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