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Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking
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Authors:
Erland Nilsson
Royal Institute of Technology (KTH), Kista, Sweden
Johnny Öberg
Royal Institute of Technology (KTH), Kista, Sweden
Published in:
· Proceeding
CODES+ISSS '04
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Pages 176-181
ACM
New York, NY
, USA
©2004
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ISBN:1-58113-937-3
doi>
10.1145/1016720.1016764
2004 Article
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· Citation Count: 12
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Tags:
clocking
combinational logic
design
gals
gpls
hot-potato
mesh
network on chip
pseudochronous
vlsi
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