An approach for integrating basic retiming and software pipelining

doi:10.1145/1017753.1017799

An approach for integrating basic retiming and software pipelining

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Authors:	Noureddine Chabini	Royal Military College of Canada, Kingston, ON, Canada
	Wayne Wolf	Princeton University, Princeton, NJ

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	· Proceeding
	EMSOFT '04 Proceedings of the 4th ACM international conference on Embedded software
	ACM New York, NY, USA ©2004 table of contents ISBN:1-58113-860-1 doi>10.1145/1017753.1017799

	2004 Article
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Tags: algorithms code size design embedded systems general instruction-level parallelism peak power performance retiming software pipelining superscalar processor system-on-chip timings vliw

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