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Floating-point sparse matrix-vector multiply for FPGAs
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Authors:
Michael deLorimier
California Institute of Technology, Pasadena, CA
André DeHon
California Institute of Technology, Pasadena, CA
Published in:
· Proceeding
FPGA '05
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Pages 75-85
ACM
New York, NY
, USA
©2005
table of contents
ISBN:1-59593-029-9
doi>
10.1145/1046192.1046203
2005 Article
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· Citation Count: 24
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Upcoming Conference:
FPGA'14
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Tags:
algorithms
algorithms
algorithms implemented in hardware
compressed sparse row
design
experimentation
floating point
fpga
performance
reconfigurable architecture
sparse matrix
sparse, structured, and very large systems
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