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Dynamic coalescing for 16-bit instructions
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Authors:
Arvind Krishnaswamy
The University of Arizona, Tucson, AZ
Rajiv Gupta
The University of Arizona, Tucson, AZ
Published in:
· Journal
ACM Transactions on Embedded Computing Systems (TECS)
TECS Homepage
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Volume 4 Issue 1, February 2005
Pages 3 - 37
ACM
New York, NY
, USA
table of contents
doi>
10.1145/1053271.1053273
2005 Article
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· Downloads (12 Months): 19
· Downloads (cumulative): 613
· Citation Count: 5
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Tags:
16-bit thumb isa
32-bit arm isa
ax instructions
code size
compilers
embedded processor
energy
instruction coalescing
performance
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