Fault tolerant bus architecture for deep submicron based processors

Full Text: PdfPdf Buy this ArticleBuy this Article
Authors: N. Venkateswaran Waran Research Foundation, Chennai, India
S. Balaji Waran Research Foundation, Chennai, India
V. Sridhar Waran Research Foundation, Chennai, India
Published in:
Cover Image
 
· Newsletter
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA) Homepage archive
Volume 33 Issue 1, March 2005
Pages 148 - 155
ACM New York, NY, USA
table of contents doi>10.1145/1055626.1055647
Fault tolerant bus architecture for deep submicron based processors Published by ACM 2005 Article
Bibliometrics Data  Bibliometrics
· Downloads (6 Weeks): 0
· Downloads (12 Months): 9
· Downloads (cumulative): 344
· Citation Count: 2


Tools and Resources

Share:

|
feedback Feedback | Switch to single page view (no tabs)

Powered by The ACM Guide to Computing Literature


The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2013 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player
The ACM Guide to Computing Literature
All Tags
Export Formats
 
 
Save to Binder