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A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
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Authors:
Alireza Hodjat
University of California, Los Angeles, CA
David D. Hwang
University of California, Los Angeles, CA
Bocheng Lai
University of California, Los Angeles, CA
Kris Tiri
University of California, Los Angeles, CA
Ingrid Verbauwhede
University of California, Los Angeles and Katholieke Universiteit Leuven
2005 Article
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Published in:
· Proceeding
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Pages 60-63
ACM
New York, NY
, USA
©2005
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ISBN:1-59593-057-4
doi>
10.1145/1057661.1057677
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Tags:
advanced encryption standard
algorithms implemented in hardware
asic
crypto-processor
cryptography
design
fpga
hardware architectures
security
security
vlsi
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