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Navigating registers in placement for clock network minimization
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Authors:
Yongqiang Lu
Tsinghua University, Beijing, China
C. N. Sze
Texas A&M University, College Station, TX
Xianlong Hong
Tsinghua University, Beijing, China
Qiang Zhou
Tsinghua University, Beijing, China
Yici Cai
Tsinghua University, Beijing, China
Liang Huang
Tsinghua University, Beijing, China
Jiang Hu
Texas A&M University, College Station, TX
2005 Article
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· Downloads (12 Months): 22
· Downloads (cumulative): 228
· Citation Count: 11
Published in:
· Proceeding
DAC '05
Proceedings of the 42nd annual Design Automation Conference
Pages 176-181
ACM
New York, NY
, USA
©2005
table of contents
ISBN:1-59593-058-2
doi>
10.1145/1065579.1065628
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Tags:
algorithms
clock network
design
design aids
low power
performance
placement
variation tolerance
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