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A design platform for 90-nm leakage reduction techniques
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Authors:
Philippe Royannez
Texas Instruments, Villeneuve-Loubet, France
Hugh Mair
Texas Instruments, Villeneuve-Loubet, France
Franck Dahan
Texas Instruments, Villeneuve-Loubet, France
Mike Wagner
Texas Instruments, Villeneuve-Loubet, France
Mark Streeter
Texas Instruments, Villeneuve-Loubet, France
Laurent Bouetel
Texas Instruments, Villeneuve-Loubet, France
Joel Blasquez
Texas Instruments, Villeneuve-Loubet, France
H. Clasen
Texas Instruments, Villeneuve-Loubet, France
G. Semino
Texas Instruments, Villeneuve-Loubet, France
Julie Dong
Texas Instruments, Villeneuve-Loubet, France
D. Scott
Texas Instruments, Villeneuve-Loubet, France
B. Pitts
Texas Instruments, Villeneuve-Loubet, France
Claudine Raibaut
Texas Instruments, Villeneuve-Loubet, France
Uming Ko
Texas Instruments, Villeneuve-Loubet, France
2005 Article
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Published in:
· Proceeding
DAC '05
Proceedings of the 42nd annual Design Automation Conference
Pages 549-550
ACM
New York, NY
, USA
©2005
table of contents
ISBN:1-59593-058-2
doi>
10.1145/1065579.1065722
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Tags:
design
design aids
leakage power management
soc design
verification
wireless application processor
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