Streamline verification process with formal property verification to meet highly compressed design cycle

Full Text: PDFPDF Buy this ArticleBuy this Article
Author: Prosenjit Chatterjee NVIDIA Corporation, Santa Clara, CA
Published in:
· Proceeding
DAC '05 Proceedings of the 42nd annual Design Automation Conference
Pages 674-677
ACM New York, NY, USA ©2005
table of contents ISBN:1-59593-058-2 doi>10.1145/1065579.1065757
Streamline verification process with formal property verification to meet highly compressed design cycle Published by ACM 2005 Article
Bibliometrics Data  Bibliometrics
· Downloads (6 Weeks): 3
· Downloads (12 Months): 15
· Downloads (cumulative): 174
· Citation Count: 2


Tools and Resources

Share:

|
feedback Feedback | Switch to single page view (no tabs)

Powered by The ACM Guide to Computing Literature


The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2013 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player
The ACM Guide to Computing Literature
All Tags
Export Formats
 
 
Save to Binder