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Effectiveness of low power dual-V
t
designs in nano-scale technologies under process parameter variations
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Authors:
Amit Agarwal
Purdue University, West Lafayette, IN
Kunhyuk Kang
Purdue University, West Lafayette, IN
Swarup K. Bhunia
Purdue University, West Lafayette, IN
James D. Gallagher
Purdue University, West Lafayette, IN
Kaushik Roy
Purdue University, West Lafayette, IN
2005 Article
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· Citation Count: 3
Published in:
· Proceeding
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Pages 14-19
ACM
New York, NY
, USA
©2005
table of contents
ISBN:1-59593-137-6
doi>
10.1145/1077603.1077609
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Tags:
algorithms
algorithms implemented in hardware
design
dual-v
t
leakage
metal gate
optimization
performance
process variation
reliability
yield
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