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Replacing global wires with an on-chip network: a power analysis
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Authors:
Seongmoo Heo
MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanović
MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Published in:
· Proceeding
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Pages 369-374
ACM
New York, NY
, USA
©2005
table of contents
ISBN:1-59593-137-6
doi>
10.1145/1077603.1077692
2005 Article
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· Citation Count: 18
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microprocessors and microcomputers
on-chip network power model
performance
pipelining
router
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vlsi
wire power model
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