A technique for low energy mapping and routing in network-on-chip architectures

doi:10.1145/1077603.1077695

A technique for low energy mapping and routing in network-on-chip architectures

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Authors:	Krishnan Srinivasan	Arizona State University, Tempe, AZ
	Karam S. Chatha	Arizona State University, Tempe, AZ

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	· Proceeding
	ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
	ACM New York, NY, USA ©2005 table of contents ISBN:1-59593-137-6 doi>10.1145/1077603.1077695

	2005 Article
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Tags: algorithms automated design core mapping design interconnections mesh topology network-on-chip performance routing

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