An alternative logic approach to implement high-speed low-power full adder cells

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Authors: Mariano Aguirre INAOE-Mexico, Puebla, Mexico
Monico Linares INAOE-Mexico, Puebla, Mexico
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· Proceeding
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Pages 166-171
ACM New York, NY, USA ©2005
table of contents ISBN:1-59593-174-0 doi>10.1145/1081081.1081125
An alternative logic approach to implement high-speed low-power full adder cells Published by ACM 2005 Article
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