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From multi-clocked synchronous processes to latency-insensitive modules
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Authors:
Jean-Pierre Talpin
INRIA - IRISA, Cedex, France
Dimitru Potop-Butucaru
INRIA - IRISA, Cedex, France
Julien Ouy
INRIA - IRISA, Cedex, France
Benoit Caillaud
INRIA - IRISA, Cedex, France
2005 Article
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Published in:
· Proceeding
EMSOFT '05
Proceedings of the 5th ACM international conference on Embedded software
Pages 282-285
ACM
New York, NY
, USA
©2005
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ISBN:1-59593-091-4
doi>
10.1145/1086228.1086279
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algorithms
compositional mapping
design tools and techniques
reliability
separate compilation
verification
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