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Bit-level partial evaluation of synchronous circuits
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Authors:
Sarah Thompson
University of Cambridge
Alan Mycroft
University of Cambridge
Published in:
· Proceeding
PEPM '06
Proceedings of the 2006 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
Pages 29 - 37
ACM
New York, NY
, USA
©2006
table of contents
ISBN:1-59593-196-1
doi>
10.1145/1111542.1111548
2006 Article
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Tags:
design
loop unrolling
partial evaluation
sequential circuits
synchronous circuits
verification
verification
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