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Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
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Authors:
K. Yamaoka
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
T. Morimoto
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
H. Adachi
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
T. Koide
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
H. J. Mattausch
Hiroshima University, Kagamiyama, Higashi-Hiroshima, Japan
2006 Article
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Published in:
· Proceeding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Pages 176 - 181
IEEE Press
Piscataway, NJ
, USA
©2006
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ISBN:0-7803-9451-8
doi>
10.1145/1118299.1118350
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Tags:
algorithms
algorithms implemented in hardware
design
gate arrays
pattern matching
performance
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