Simultaneous block and I/O buffer floorplanning for flip-chip design

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Authors: Chih-Yang Peng National Taiwan University, Taipei, Taiwan
Wen-Chang Chao National Taiwan University, Taipei, Taiwan
Yao-Wen Chang National Taiwan University, Taipei, Taiwan
Jyh-Herng Wang Faraday Technology Corporation, Hsinchu, Taiwan
Simultaneous block and I/O buffer floorplanning for flip-chip design 2006 Article
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· Proceeding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Pages 213 - 218
IEEE Press Piscataway, NJ, USA ©2006
table of contents ISBN:0-7803-9451-8 doi>10.1145/1118299.1118357

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