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Delay variation tolerance for domino circuits
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Authors:
Kai-Chiang Wu
National Tsing Hua University, Hsinchu, Taiwan
Cheng-Tao Hsieh
National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang
National Tsing Hua University, Hsinchu, Taiwan
Published in:
· Proceeding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Press
Piscataway, NJ
, USA
©2006
table of contents
ISBN:0-7803-9451-8
doi>
10.1145/1118299.1118389
2006 Article
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· Citation Count: 0
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Tags:
automatic synthesis
design
input/output circuits
performance
placement and routing
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