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Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

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Authors: Jae-Gon Lee Korea Advanced Institute of Science and Technology, Daejeon, Korea
Wooseung Yang R&D Center, Dynalith Systems Co., Ltd., Daejeon, Korea
Young-Su Kwon R&D Center, Dynalith Systems Co., Ltd., Daejeon, Korea
Young-Il Kim Korea Advanced Institute of Science and Technology, Daejeon, Korea
Chong-Min Kyung Korea Advanced Institute of Science and Technology, Daejeon, Korea
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks Published by ACM 2005 Article
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· Proceeding
ASP-DAC '05 Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ACM New York, NY, USA ©2005
table of contents ISBN:0-7803-8737-6 doi>10.1145/1120725.1120921

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