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This paper extends the depth first search (DFS) used in the previously proposed witness string method for generating efficient test vectors. A state pruning method is added that exploits different search heuristics in simultaneous searches. Using an IBM Power4 multiprocessor system with the Berkeley Active Message library, we show that this new method of state pruning is efficient and produces quantitatively better witness strings compared to both pure and guided DFS.
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Author image not provided  Ying Chen

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Dennis Abts Dennis Abts

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David J. Lilja David J. Lilja

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top of pageREFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. Abts, Y. Chen and David J. Lilja, "Heuristics for Complexity-Effective Verification of a Cache Coherence Protocol Implementation", Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 03--04, November 2003.
 
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H. Sivaraj and G. Gopalakrishnan, "Random Walk Based Heuristic Algorithms for Distributed Memory Model Checking", 2nd International Workshop on Parallel and Distributed Model Checking (PDMC'03), Boulder, Colorado, USA, July 2003
 
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Y. Chen, D. Abts, D. J. Lilja, "State Pruning for Generating Efficient Test Vectors", Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 04--05, July 2004

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Title ASP-DAC '05 Proceedings of the 2005 Asia and South Pacific Design Automation Conference table of contents
General Chair Ting-Ao Tang Fudan University, Shanghai, P. R. China
Pages 1196-1199
Publication Date2005-01-18 (yyyy-mm-dd)
Sponsors SIGDA ACM Special Interest Group on Design Automation
Chinese Institute of Electronics
Fudan University
IEEE Beijing Section
IEEE CAS
IEEE SSCS Shanghai Chapter
Shanghai IC Industry Association
PublisherACM New York, NY, USA ©2005
ISBN: 0-7803-8737-6 doi>10.1145/1120725.1120939
Conference ASPDACAsia and South Pacific Design Automation Conference ASPDAC logo
Overall Acceptance Rate 667 of 1,877 submissions, 36%
Year Submitted Accepted Rate
ASP-DAC '06 424 179 42%
ASP-DAC '07 408 131 32%
ASP-DAC '08 350 122 35%
ASP-DAC '09 355 116 33%
ASPDAC '10 340 119 35%
Overall 1,877 667 36%

APPEARS IN
Hardware Design

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top of pageTable of Contents

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Table of Contents
SESSION: Keynote address
Silicon compilation: the answer to reducing IC development costs
Rajeev Madhavan
Pages: 1-2
doi>10.1145/1120725.1120728
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Developing today's increasingly large and complex digital integrated circuit (IC) and system-on-chip (SoC) devices is becoming cost-prohibitive in terms of engineering resources and development time. Packing the advanced functionality of a microprocessor, ...
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Design at the end of the silicon roadmap
Jan M. Rabaey
Pages: 1-2
doi>10.1145/1120725.1120729
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Scaling of silicon integrated technology into the deep sub-100 nm space brings with it a number of formidable challenges to the designer. Issues such as design complexity, power dissipation, process variability and reliability are challenging the traditional ...
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The development of integrated circuit industry in China
Zhenghua Jiang
Pages: 1-2
doi>10.1145/1120725.1120727
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The first semiconductor device of China was invented in Shanghai by Fudan University. The China made chips had been equipped national missiles in 1960s. However, The progress of technology was interrupted in the period of "cultural revolution". Since ...
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SESSION: Tree construction and buffering
Patrick H. Madden, Cheng-Kok Koh
The polygonal contraction heuristic for rectilinear Steiner tree construction
Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan
Pages: 1-6
doi>10.1145/1120725.1120731
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Motivated by VLSI/ULSI routing applications, we present a heuristic for rectilinear Steiner minimal tree (RSMT) construction. We transform a rectilinear minimum spanning tree (RMST) into an RSMT by a novel method called polygonal contraction. Experimental ...
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An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan
Pages: 7-12
doi>10.1145/1120725.1120732
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Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing ...
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Making fast buffer insertion even faster via approximation techniques
Zhuo Li, C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Pages: 13-18
doi>10.1145/1120725.1120733
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As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing electrical violations. Consequently, buffer insertion is needed on tens of thousands ...
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Concurrent flip-flop and buffer insertion with adaptive blockage avoidance
Zhong-Ching Lu, Ting-Chi Wang
Pages: 19-22
doi>10.1145/1120725.1120734
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Given a routing tree for a multi-pin net, two algorithms extending the van Ginneken algorithm [3] for concurrent flip-flop and buffer insertion were presented in [5]. One algorithm called MiLa targets at minimizing the latency, and the other algorithm ...
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Buffering global interconnects in structured ASIC design
Tianpei Zhang, Sachin S. Sapatnekar
Pages: 23-26
doi>10.1145/1120725.1120735
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Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However via-programmable designs must prefabricate and ...
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SESSION: System level design methodology for network-on-chip
X. Sharon Hu, Soonhoi Ha
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Srinivasan Murali, Luca Benini, Giovanni De Micheli
Pages: 27-32
doi>10.1145/1120725.1120737
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Networks on Chips (NoCs) have evolved as the communication design paradigm of future Systems on Chips (SoCs). In this work we target the NoC design of complex SoCs with heterogeneous processor/memory cores, providing Quality-of-Service ...
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Time and energy efficient mapping of embedded applications onto NoCs
César Marcon, André Borin, Altamiro Susin, Luigi Carro, Flávio Wagner
Pages: 33-38
doi>10.1145/1120725.1120738
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This work analyzes, the mapping of applications onto generic regular Networks-on-Chip (NoCs). Cores must be placed considering communication requirements so as to minimize the overall application execution time and energy consumption. We expand previous ...
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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou
Pages: 39-44
doi>10.1145/1120725.1120739
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Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling ...
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System-level communication modeling for network-on-chip synthesis
Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski
Pages: 45-48
doi>10.1145/1120725.1120740
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As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are becoming the integral part of system design flows. The key to the success of any design flow are well-defined ...
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MAIA: a framework for networks on chip generation and verification
Luciano Ost, Aline Mello, José Palma, Fernando Moraes, Ney Calazans
Pages: 49-52
doi>10.1145/1120725.1120741
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The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. ...
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SESSION: Test and DFT (1)
Alex Orailoglu, Xiaoqing Wen
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
Pages: 53-58
doi>10.1145/1120725.1120743
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This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is proposed. Theoretic analysis for this encoder is presented ...
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Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
Pages: 59-64
doi>10.1145/1120725.1120744
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This paper presents a test compression method that effectively derives the capability of a run-length based encoding. The method employs two techniques: scan polarity adjustment and pinpoint test relaxation. Given a test set for a full-scan circuit, ...
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Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Jin-Fu Li
Pages: 65-70
doi>10.1145/1120725.1120745
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With the increasing demand for high-performance networking application, network components such as network interfaces and routers are built in dedicated hardware modulars. Content addressable memories (CAMs) play an important role in the network components. ...
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SPIN-PAC: test compaction for speed-independent circuits
Feng Shi, Yiorgos Makris
Pages: 71-74
doi>10.1145/1120725.1120746
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SPIN-PAC is a static test compaction method for Speed-Independent circuits. We demonstrate how the test sets can be compacted by combining multiple consecutive test vectors within a test sequence into a vector pair of higher Hamming distance, and by ...
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A Huffman-based coding with efficient test application
Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue
Pages: 75-78
doi>10.1145/1120725.1120747
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Test compression / decompression method using variable length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding imposes slow test application, ...
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SESSION: (Special session) DFM
Embedded tutorial I: design for manufacturability
Vijay Pitchumani
Pages: 1-1
doi>10.1145/1120725.1120749
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DFM (Design for Manufacturability) has recently become a buzzword; it excites passion in semiconductor process, design, EDA and manufacturing circles. What is all this hype about?This tutorial reviews DFM, the ugly cousin of technology scaling, in a ...
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ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress
Rouying Zhan, Haolu Xie, Haigang Feng, Albert Wang
Pages: 79-82
doi>10.1145/1120725.1120750
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On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to ...
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A new method for model based frugal OPC
Xiaolang Yan, Ye Chen, Zheng Shi, Yue Ma
Pages: 83-86
doi>10.1145/1120725.1120751
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Improvements on Resolution Enhancement Technologies (RETs) enable minimum feature size of IC to shrink consistently with Moore's Law. However growing mask data volume also tremendously increases manufacture cost. The cost increase is partially due to ...
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SESSION: Clock, power grid and thermal analysis and optimization
Xiaodong Yang, Eli Chiprout
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up
Yong Zhan, Sachin S. Sapatnekar
Pages: 87-92
doi>10.1145/1120725.1120753
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Temperature-related effects are critical in determining both the performance and reliability of VLSI circuits. Accurate and efficient estimation of the temperature distribution corresponding to a specific circuit layout is indispensable in physical design ...
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Analysis of buffered hybrid structured clock networks
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
Pages: 93-98
doi>10.1145/1120725.1120754
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This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical analysis methods to reduce the circuit complexity and speedup the simulation. ...
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Clock network minimization methodology based on incremental placement
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
Pages: 99-102
doi>10.1145/1120725.1120755
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In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size. Traditional design methodologies usually let the clock router to undertake ...
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A multi-level transmission line network approach for multi-giga hertz clock distribution
Hongyu Chen, Chung-Kuan Cheng
Pages: 103-106
doi>10.1145/1120725.1120756
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In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and mesh [2,15,18,19] were proposed to distribute the clock signal with a balanced ...
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Gibbs sampling in power grid analysis
Zhixin Tian, Huazhong Yang, Rong Luo
Pages: 107-110
doi>10.1145/1120725.1120757
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Power grid plays an important role in determining circuit performance, and the accuracy and efficiency of power grid analysis algorithm has become critical in timing, power and noise estimation of modern integrated circuits. In this paper a stochastic ...
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A wideband hierarchical circuit reduction for massively coupled interconnects
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
Pages: 111-114
doi>10.1145/1120725.1120758
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We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vector potential equivalent circuit) model, which not only enables the passive ...
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SESSION: Routing and interconnects
Martin D. F. Wong, Tong Jing
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem
Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
Pages: 115-120
doi>10.1145/1120725.1120786
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This paper presents a novel global routing algorithm, AT-PO-GR, to minimize the routing area under both congestion, timing, and RLC crosstalk constraints. The proposed algorithm is consisted of three key parts: (1) timing and congestion optimization; ...
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Thermal-driven multilevel routing for 3-D ICs
Jason Cong, Yan Zhang
Pages: 121-126
doi>10.1145/1120725.1120787
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3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A critical issue in 3-D circuit design is heat dissipation. In this paper we ...
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Wave-pipelined on-chip global interconnect
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Pages: 127-132
doi>10.1145/1120725.1120788
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A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal propagation path and a single type of 1-input gate(inverter), a wave-pipelined ...
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Evaluation of on-chip transmission line interconnect using wire length distribution
Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
Pages: 133-138
doi>10.1145/1120725.1120789
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On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which ...
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SESSION: System level modeling and embedded software
Tim Tuan, S. K. Nandy
A formalism for functionality preserving system level transformations
Samar Abdi, Daniel Gajski
Pages: 139-144
doi>10.1145/1120725.1120791
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With the rise in complexity of modern systems, designers are spending a significant time on modeling at the system level of abstraction. This paper introduces Model Algebra, a formalism built on top of system level design languages, that can be used ...
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Embedded software generation from system level specification for multi-tasking embedded systems
KiSeun Kwon, YoungMin Yi, DoHyung Kim, SoonHoi Ha
Pages: 145-150
doi>10.1145/1120725.1120792
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In this paper we present a new design flow in which embedded software code is generated from system level specification of multi-tasking embedded system, both for simulation and implementation. The generated software has a layered structure using virtual ...
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Scheduler implementation in MP SoC design
Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
Pages: 151-156
doi>10.1145/1120725.1120793
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In the design of a heterogeneous multiprocessor system on chip, we face a new design problem; scheduler implementation. In this paper, we present an approach to implementing a static scheduler, which controls all the task executions and communication ...
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Optimizing embedded applications using programmer-inserted hints
G. Chen, M. Kandemir
Pages: 157-160
doi>10.1145/1120725.1120794
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This paper explores the possibility of exploiting programmer-inserted hints in the application code to improve performance beyond what could be achieved using an optimizing compiler. These hints can be beneficial in two scenarios: (1) when compiler analysis ...
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Static analysis and automatic code synthesis of flexible FSM model
Dohyung Kim, Soonhoi Ha
Pages: 161-165
doi>10.1145/1120725.1120795
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To describe complex control modules, the following four features are requested for extended FSM models: concurrency, compositionality, static analyzability, and automatic code synthesis capability. In our codesign environment we use a new FSM extension ...
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SESSION: Test and DFT (2)
Kwang-Ting (Tim) Cheng, Shiyi Xu
Constraint extraction for pseudo-functional scan-based delay testing
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
Pages: 166-171
doi>10.1145/1120725.1120797
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Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults that are untestable in the functional mode while testable in the test mode. ...
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Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Hafizur Rahaman, Debesh K. Das
Pages: 172-177
doi>10.1145/1120725.1120798
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Testable design for detecting stuck-at and bridging faults in Programmable Logic Arrays (PLAs) based on Double Fixed-Polarity Reed-Muller Expression (DFPRM) is proposed. DFPRMs are generalized expressions of FPRM. It has advantages of compactness and ...
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Propagation delay fault: a new fault model to test delay faults
Xijiang Lin, Janusz Rajski
Pages: 178-183
doi>10.1145/1120725.1120799
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A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of ...
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Oscillation ring based interconnect test scheme for SOC
Katherine Shu-Min Li, Chung Len Lee, Chauchin Su, Jwu E Chen
Pages: 184-187
doi>10.1145/1120725.1120800
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We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation ...
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Bridging fault testability of BDD circuits
Junhao Shi, Görschwin Fey, Rolf Drechsler
Pages: 188-191
doi>10.1145/1120725.1120801
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In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be formulated in terms of symbolic BDD operations. By this, test pattern generation can be ...
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SESSION: TCAD
Kenji Nishi, Changhong Dai
Yield driven gate sizing for coupling-noise reduction under uncertainty
Debjit Sinha, Hai Zhou
Pages: 192-197
doi>10.1145/1120725.1120803
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This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make ...
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Maze routing with OPC consideration
Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang
Pages: 198-203
doi>10.1145/1120725.1120804
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As the technology of manufacturing process continues to advance, the process variation becomes more and more serious in nanometer designs. Optical proximity correction (OPC) is employed to correct the process variation of the diffraction effect. To obtain ...
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Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm
Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi
Pages: 204-207
doi>10.1145/1120725.1120805
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In this paper, we present an automatic parameter extraction method with the GA (Genetic Algorithm) for surface-potential-based MOSFET models such as HiSIM (Hiroshima-university STARC IGFET Model). The method employs a two-stage extraction procedure operating ...
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Substrate resistance extraction with direct boundary element method
Xiren Wang, Wenjian Yu, Zeyi Wang
Pages: 208-211
doi>10.1145/1120725.1120806
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It is important to model the substrate coupling for mixed-signal circuit designs today. This paper presents the direct boundary element method (BEM) for substrate resistance calculation, where only the boundary of substrate region is discretized. Firstly, ...
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An efficient combinationality check technique for the synthesis of cyclic combinational circuits
Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang
Pages: 212-215
doi>10.1145/1120725.1120807
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It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits ...
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Library cell layout with Alt-PSM compliance and composability
Ke Cao, Puneet Dhawan, Jiang Hu
Pages: 216-219
doi>10.1145/1120725.1120808
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The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET). The difficulty and feasibility of deploying the RET such as Alternating ...
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Forward discrete probability propagation method for device performance characterization under process variations
Rasit Onur Topaloglu, Alex Orailoglu
Pages: 220-223
doi>10.1145/1120725.1120809
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Process variations are becoming influential at the device level in deep sub-micron and sub-wavelength design regimes, whereas they used to be a few generations away only influential at circuit level. Process variations cause device performance parameters, ...
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SESSION: Simulation and modeling techniques for RF/analog circuits
Jaijeet Roychowdhury, Yici Cai
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
Pages: 224-229
doi>10.1145/1120725.1120811
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This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed s-domain hierarchical modeling and analysis method [27]. Theoretically, we show ...
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Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams
Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Geoges Gielen
Pages: 230-235
doi>10.1145/1120725.1120812
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This paper presents a new method to perform efficient first-order symbolic sensitivity analysis of analog circuits by direct differentiation of symbolic expressions stored as element-coefficient diagrams (ECDs). An ECD is a compact graphical representation ...
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A new approach for ring oscillator simulation using the harmonic balance method
Xiaochun Duan, Kartikeya Mayaram
Pages: 236-239
doi>10.1145/1120725.1120813
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A novel approach for simulating the periodic steady state of ring oscillators with the harmonic balance method is described. A single delay cell based equivalent circuit is simulated and used to determine the response of the overall circuit. This results ...
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Efficient transient simulation for transistor-level analysis
Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
Pages: 240-243
doi>10.1145/1120725.1120814
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In this paper, we introduce an efficient transistor level simulation tool with SPICE-accuracy for deep-submicron(DSM) VLSI circuits with strong coupling effects. The new approach uses multigrid for large networks of power/ground, clock and signal interconnect. ...
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Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits
Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou
Pages: 244-249
doi>10.1145/1120725.1120815
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Recently model order reduction techniques for second-order systems have obtained many research interests for the simulation of RCS interconnect circuits employing susceptance elements. In this paper, we propose a Block SAPOR (Block Second-order Arnoldi ...
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Block based statistical timing analysis with extended canonical timing model
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Pages: 250-253
doi>10.1145/1120725.1120816
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Block based statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path reconvergence. To the best of our knowledge, no good solution is available handling ...
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SESSION: Logic synthesis
Jianwen Zhu, Sikun Li
FSM re-engineering and its application in low power state encoding
Lin Yuan, Gang Qu, Tiziano Villa, Alberto Sangiovanni-Vincentelli
Pages: 254-259
doi>10.1145/1120725.1120844
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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then re-construct a functionally equivalent ...
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Post-layout logic duplication for synthesis of domino circuits with complex gates
Aiqun Cao, Ruibing Lu, Cheng-Kok Koh
Pages: 260-265
doi>10.1145/1120725.1120845
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Logic duplication to resolve the logic reconvergent paths problem encountered in Domino logic synthesis is expensive in terms of area and power. In this paper, we propose a combined logic duplication minimization and technology mapping scheme for Domino ...
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Detecting support-reducing bound sets using two-cofactor symmetries
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
Pages: 266-271
doi>10.1145/1120725.1120846
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Detecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting ...
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Synthesis of quantum logic circuits
Vivek V. Shende, Stephen S. Bullock, Igor L. Markov
Pages: 272-275
doi>10.1145/1120725.1120847
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The pressure of fundamental limits on classical computation and the promise of exponential speedups from quantum effects have recently brought quantum circuits to the attention of the EDA community [10, 17, 4, 16, 9]. We discuss efficient circuits to ...
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STACCATO: disjoint support decompositions from BDDs through symbolic kernels
Stephen Plaza, Valeria Bertacco
Pages: 276-279
doi>10.1145/1120725.1120848
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A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component functions have no common inputs. The decomposition of a function is desirable ...
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SESSION: System level architecture design
Sreedhar Natarrajan, Soo-Ik Chae
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
Oliver Schliebusch, A. Chattopadhyay, D. Kammler, G. Ascheid, R. Leupers, H. Meyr, Tim Kogel
Pages: 280-285
doi>10.1145/1120725.1120850
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Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility ...
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A processor core synthesis system in IP-based SoC design
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Pages: 286-291
doi>10.1145/1120725.1120851
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This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs ...
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Speed and voltage selection for GALS systems based on voltage/frequency islands
Koushik Niyogi, Diana Marculescu
Pages: 292-297
doi>10.1145/1120725.1120852
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Due to increasing clock speeds and shrinking technologies, distributing a single global clock signal throughout a chip is becoming a difficult and challenging proposition. In this paper, we address the problem of energy optimal local speed and voltage ...
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A system-level approach to hardware reconfigurable systems
Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich
Pages: 298-301
doi>10.1145/1120725.1120853
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There is trend towards networked and distributed hardware reconfigurable systems, complicating the design process at the system-level. This paper will provide a solution to the problem of design space exploration for such embedded systems of the next ...
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High-level synthesis for DSP applications using heterogeneous functional units
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin H.-M. Sha
Pages: 302-304
doi>10.1145/1120725.1120854
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This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an important problem is how to assign a proper FU type to ...
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SESSION: Test and verification
Yinghua Min, Alan J. Hu
Evaluation of the statistical delay quality model
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
Pages: 305-310
doi>10.1145/1120725.1120856
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In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal ...
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Fault tolerant nanoelectronic processor architectures
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Pages: 311-316
doi>10.1145/1120725.1120857
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In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment that is characterized by high and time varying fault rates. The proposed ...
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An efficient control-oriented coverage metric
Shireesh Verma, Kiran Ramineni, Ian G. Harris
Pages: 317-322
doi>10.1145/1120725.1120858
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Coverage metrics, which evaluate the ability of a test sequence to detect design faults, are essential to the validation process. A key source of difficulty in determining fault detection is that the control flow path traversed in the presence of a fault ...
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An observability measure to enhance statement coverage metric for proper evaluation of verification completeness
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Pages: 323-326
doi>10.1145/1120725.1120859
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Simulation based validation approaches are still the primary workhorse for solving the verification problem of getting the initial HDL description correct, especially for large scaled designs. However, most of existing code coverage metrics do not address ...
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Tightly integrate dynamic verification with formal verification: a GSTE based approach
Jin Yang, Avi Puder
Pages: 327-330
doi>10.1145/1120725.1120860
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GSTE (Generalized Symbolic Trajectory Evaluation) is a high capacity formal verification technology that has been successfully applied to verifying complex Intel designs with tens of thousands of state elements. In this paper, we extend the use of GSTE ...
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SESSION: Special session
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
C. K. Cheng, Steve Lin, Andrew Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
Pages: 1-1
doi>10.1145/1120725.1120862
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The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases ...
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SESSION: Placement techniques
Xianlong Hong, Ting-Chi Wang
On structure and suboptimality in placement
Satoshi Ono, Patrick H. Madden
Pages: 331-336
doi>10.1145/1120725.1120864
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Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we present a novel placement approach that successfully identifies regularity, and obtains ...
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Optimal placement by branch-and-price
Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden
Pages: 337-342
doi>10.1145/1120725.1120865
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Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected transistors. The placement problem is NP-Complete for even simple metrics.In ...
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Detailed placement for improved depth of focus and CD control
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
Pages: 343-348
doi>10.1145/1120725.1120866
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Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in subwavelength lithography. However, as focus levels change during manufacturing, CDs at a given "legal" ...
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Floorplan management: incremental placement for gate sizing and buffer insertion
Chen Li, Cheng-Kok Koh, Patrick H. Madden
Pages: 349-354
doi>10.1145/1120725.1120867
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Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental changes to the layout and netlist due to physical synthesis techniques without ...
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SESSION: Security processor design
Lorena Anghel, Steve Lin
Low-power techniques for network security processors
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
Pages: 355-360
doi>10.1145/1120725.1120869
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In this paper, we present several techniques for low-power design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments ...
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A configurable AES processor for enhanced security
Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
Pages: 361-366
doi>10.1145/1120725.1120870
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We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to 219 different AES block cipher schemes within a reasonable hardware cost. Data can be encrypted not only with secret keys ...
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Power estimation starategies for a low-power security processor
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang
Pages: 367-371
doi>10.1145/1120725.1120871
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In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. ...
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Design and test of a scalable security processor
Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Pages: 372-375
doi>10.1145/1120725.1120872
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This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed ...
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System-level design space exploration for security processor prototyping in analytical approaches
Yung Chia Lin, Chung Wen Huang, Jenq Kuen Lee
Pages: 376-380
doi>10.1145/1120725.1120873
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The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration of design spaces. In this paper, we present an analytical modeling strategy ...
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SESSION: (Special session) embedded tutorial II
Lei He
Leakage power: trends, analysis and avoidance
David Blaauw, Anirudh Devgan, Farid Najm
Pages: 1-1
doi>10.1145/1120725.1120875
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Leakage power is emerging as a key challenge in IC design. Leakage is increasingly exponentially with each technology generation and is expected to become the dominant part of total power. Device threshold voltage scaling, shrinking device dimensions, ...
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SESSION: (Special session) CAD for microarchitecture designs
Hannah Honghua Yang
Challenges to covering the high-level to silicon gap
Bill Grundmann
Pages: 1-1
doi>10.1145/1120725.1120877
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Silicon architects have a difficult task. They have to translate a high-level product desire into a lower-level description for silicon implementation. They are required to balance their own creativity, project schedule, solution cost, and the degree ...
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Opportunities and challenges for better than worst-case design
Todd Austin, Valeria Bertacco, David Blaauw, Trevor Mudge
Pages: 2-7
doi>10.1145/1120725.1120878
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The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, uncertainty in environmental and fabrication conditions, and single-event ...
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Microarchitecture evaluation with floorplanning and interconnect pipelining
Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
Pages: 8-15
doi>10.1145/1120725.1120879
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As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple cycles will be necessary to communicate global signals across the chip. Thus, ...
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SESSION: University design contest
Xiaoyang Zeng, Makoto Ikeda, Lin Yang
TERPS: the embedded reliable processing system
Hongxia Wang, Samuel Rodriguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce Jacob
Pages: 1-2
doi>10.1145/1120725.1120886
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TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically checkpointing processor state into a special safe-storage ...
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AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow
D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, A. Thanailakis
Pages: 3-4
doi>10.1145/1120725.1120887
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The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of ...
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Standard CMOS technology on-chip inductors with pn junctions substrate isolation
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao
Pages: 5-6
doi>10.1145/1120725.1120888
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New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the reverse bias voltage to pn junctions, the lower substrate ...
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A bandwidth efficient subsampling-based block matching architecture for motion estimation
Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang
Pages: 7-8
doi>10.1145/1120725.1120889
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We have developed a new pel subsampling-based search hardware for motion estimation called quartet-pel motion estimation (QME). The memory access of search range memory can be reduced to 25%. The computational complexity can also be reduced to 25% with ...
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Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process
Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
Pages: 9-10
doi>10.1145/1120725.1120890
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We develop and measure a 8:1 multiplexer in a CMOS 0.18μm process. We design the hybrid multiplexer based on a prior detailed performance evaluation both of CMOS static and current mode logic circuits, and build a hybrid structure. The fabricated ...
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A design of high speed double precision floating point adder using macro modules
Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li
Pages: 11-12
doi>10.1145/1120725.1120891
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Based on SMIC 0.18 μm 1.8v six-layer-metal CMOS process, we implement a 64-bit high speed pipelined floating point adder which satisfied IEEE 754 standard. After the critical path analysis of the pipelined structure, we custom design three macro modules ...
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A low-power video segmentation LSI with boundary-active-only architecture
Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
Pages: 13-14
doi>10.1145/1120725.1120892
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We designed a cell-network-based video segmentation test-chip in 0.35μm CMOS technology including a power reduction technique which activates only boundary cells of currently grown regions. The effectiveness of the proposed technique is confirmed ...
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The design and implementation of a DVB receiving chip with PCI interface
Xu Ningyi, Li Shaohua, Yu Wei, He Guanghui, Zhang Hao, Luo Fei, Zhou Zucheng
Pages: 15-16
doi>10.1145/1120725.1120893
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A DVB receiving chip with PCI interface for PC is presented. The chip supports DVB protocols and integrates useful interfaces, including I2C, SmartCard and PCI. A card with this chip could change PC into digital TV terminal. The architecture ...
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Design and implementation of an SDH high-speed switch
De_Hui Zhang, Quan_Liang Zhao, Jun-Gang Han
Pages: 17-18
doi>10.1145/1120725.1120894
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In this shot paper, we propose a design of SDH High-Speed Switch, which can switch 16x16 STM-16 streams with speed at 2.488 Gbit/s. In this design a novel fabric structure was used to perform non-blocking connection of STM-1 data in any timeslot of 16-bit ...
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Design of vehicle position tracking system using short message services and its implementation on FPGA
Arias Tanti Hapsari, Eniman Y Syamsudin, Imron Pramana
Pages: 19-20
doi>10.1145/1120725.1120895
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This paper describes the design of a system that can give information of vehicle position everytime there's a request for it. The information of vehicle position is gained from GPS and it is transmitted using Short Message Services. The system is designed ...
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Design of A 2.4-GHz integrated frequency synthesizer
Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun
Pages: 21-22
doi>10.1145/1120725.1120896
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A 2.4-GHz integrated frequency synthesizer of PLL-based in 0.35-μm RF process is presented. A fully integrated cross-coupled LC VCO of low phase noise is implemented. Prescaler accompanied with phase-switching is used to eliminate the glitch. The ...
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An improved test access mechanism structure and optimization technique in system-on-chip
Feng Jianhua, Long Jieyi, Xu Wenhua, Ye Hongfei
Pages: 23-24
doi>10.1145/1120725.1120897
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This paper presents a new test access mechanism (TAM) architecture and optimization method based on an improved flexible-width test bus. The method is first to set up the test time lower bound that is not depends on TAM architecture, then to construct ...
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SESSION: (Special session) embedded tutorial III
Howard Chen, Lei He
Designing reliable circuit in the presence of soft errors
Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin
Pages: 1-1
doi>10.1145/1120725.1120905
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As technology scales, with ever shrinking geometries and higher density circuits, the issue of soft errors and reliability in a complex chip design is becoming a challenging design criterion. Soft errors are caused by radiation, which directly or indirectly ...
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SESSION: Design optimization for high-performance digital circuits
Eli Chiprout, Zheng Shi
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen
Pages: 381-386
doi>10.1145/1120725.1120881
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Simultaneous gate-sizing with multiple Vt assignment for delay and power optimization is a complicated task in modern custom designs. In this work, we make the key contribution of a novel gate-sizing and multi-Vt assignment technique ...
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Effective analytical delay model for transistor sizing
Zhaojun Wo, Israel Koren
Pages: 387-392
doi>10.1145/1120725.1120882
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This paper describes an analytical delay model for transistor sizing. Two primitives are selected to be mapped for computing gate delay. These primitives model the short-channel effect and body effect in deep submicron CMOS circuits. A mapping algorithm ...
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Achieving continuous VT performance in a dual VT process
Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan
Pages: 393-398
doi>10.1145/1120725.1120883
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In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this ...
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Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment
Dongwoo Lee, David Blaauw, Dennis Sylvester
Pages: 399-404
doi>10.1145/1120725.1120884
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With process scaling runtime leakage current, when the circuit is operating, has become a major concern in addition to traditional standby mode leakage. In this paper we propose a new leakage reduction method that specifically targets runtime leakage ...
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SESSION: Floorplanning and partitioning
Yao-Wen Chang, Yoji Kajitani
Floorplanning for 3-D VLSI design
Lei Cheng, Liang Deng, Martin D. F. Wong
Pages: 405-411
doi>10.1145/1120725.1120899
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In this paper we present a floorplanning algorithm for 3-D ICs. The problem can be formulated as that of packing a given set of 3-D rectangular blocks while minimizing a suitable cost function. Our algorithm is based on a generalization of the classical ...
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Optimal redistribution of white space for wire length minimization
Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
Pages: 412-417
doi>10.1145/1120725.1120900
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Existing floorplanning algorithms compact blocks to the left and bottom. Although the compaction obtains an optimal area, it may not be good to meet other objectives such as minimizing total wire length which is the first-order objective. It is not known ...
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Crowdedness-balanced multilevel partitioning for uniform resource utilization
Yongseok Cheon, Martin D. F. Wong
Pages: 418-423
doi>10.1145/1120725.1120901
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In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitioned block is proportional to the logic occupation and the interconnections ...
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Partitioning and placement for buildable QCA circuits
Ramprasad Ravichandran, Mike Niemier, Sung Kyu Lim
Pages: 424-427
doi>10.1145/1120725.1120902
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Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemical molecules. In this paper, we present partitioning and placement algorithms ...
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PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits
Chanseok Hwang, Massoud Pedram
Pages: 428-431
doi>10.1145/1120725.1120903
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In this paper, we present a new performance-driven multilevel partitioning algorithm, which calculates the timing gain of a move in the move-based partitioning strategies based on the aggregation of preferred signal directions. In addition, we propose ...
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SESSION: Advances in SAT technology and application
Masahiro Fujita, Jeremy Levitt
MUP: a minimal unsatisfiability prover
Jinbo Huang
Pages: 432-437
doi>10.1145/1120725.1120907
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After establishing the unsatisfiability of a SAT instance encoding a typical design task, there is a practical need to identify its minimal unsatisfiable subsets, which pinpoint the reasons for the infeasibility of the design. Due to the potentially ...
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Integration of supercubing and learning in a SAT solver
Domagoj Babić, Alan J. Hu
Pages: 438-444
doi>10.1145/1120725.1120908
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Learning is an essential pruning technique in modern SAT solvers, but it exploits a relatively small amount of information that can be deduced from the conflicts. Recently a new pruning technique called supercubing was proposed [1]. Supercubing can exploit ...
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Dynamic symmetry-breaking for improved Boolean optimization
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
Pages: 445-450
doi>10.1145/1120725.1120909
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With impressive progress in Boolean Satisfiability (SAT) solving and several extensions to pseudo-Boolean (PB) constraints, many applications that use SAT, such as high-performance formal verification techniques are still restricted to checking satisfiability ...
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A fast counterexample minimization approach with refutation analysis and incremental SAT
Shengyu Shen, Ying Qin, SiKun Li
Pages: 451-454
doi>10.1145/1120725.1120910
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It is a hotly research topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. BFL algorithm is the most effective Counterexample minimization algorithm compared to all other approaches, but its run time overhead ...
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Sequential equivalence checking using cuts
Wei Huang, PuShan Tang, Min Ding
Pages: 455-458
doi>10.1145/1120725.1120911
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This paper presents an algorithm which is an improvement of Van Eijk's Algorithm[5] by incorporating a cutpoints technique[8]. Combinational verification often uses the technique to convert large scale circuits to several small ones, which will be verified ...
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SESSION: Analysis and simulation techniques
Richard Shi, Koichiro Mashiko
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise
Xiaolue Lai, Yayun Wan, Jaijeet Roychowdhury
Pages: 459-464
doi>10.1145/1120725.1120913
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Phase-locked loops (PLLs) are widely used in electronic systems. As PLL malfunction is one of the most important factors in re-fabs of SoCs, fast simulation of PLLs to capture non-ideal behavior accurately is an immediate, pressing need in the semiconductor ...
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Hierarchical analysis of process variation for mixed-signal systems
Fang Liu, Sule Ozev
Pages: 465-470
doi>10.1145/1120725.1120914
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Increasing process variability necessitates reliable analysis of its effects on circuit performance not only at the top level but also at intermediate levels. Mixed-signal circuits with multiple hierarchical layers, multiple parameters, and complex functional ...
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A novel wavelet method for noise analysis of nonlinear circuits
Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou
Pages: 471-476
doi>10.1145/1120725.1120915
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In this paper, a novel wavelet method is proposed for noise analysis of nonlinear circuits. Compared with the existing algorithms capable of accessing circuit performance in the present of noise, the proposed method presents several merits. First, it ...
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An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels
Mengmeng Ding, Glenn Wolfe, Ranga Vemuri
Pages: 477-482
doi>10.1145/1120725.1120916
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In this paper, we present an error-driven adaptive sampling algorithm called adaptive grid refinement (AGR) algorithm to automatically generate performance macromodels for analog circuits. Starting from samples on a coarse grid, the AGR algorithm builds ...
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SESSION: Interconnect modeling and analysis and system level design methodology
Charlie Chung-Ping Chen, Yici Cai
Partial reluctance based circuit simulation is efficient and stable
Yu Du, Wayne Dai
Pages: 483-488
doi>10.1145/1120725.1120918
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Partial reluctance K, the inversion of partial inductance L, is proposed by Devgan et al to capture the on-chip inductance effect [3]. Partial reluctance based circuit simulation is efficient and stable because it is believed that ...
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SAGA: synthesis technique for guaranteed throughput NoC architectures
Krishnan Srinivasan, Karam S. Chatha
Pages: 489-494
doi>10.1145/1120725.1120919
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We present SAGA, a novel genetic algorithm (GA) based technique for synthesis of custom NoC architectures that support guaranteed throughput traffic. The technique accepts as input a communication trace graph, amount of data, period, and deadline for ...
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Automated throughput-driven synthesis of bus-based communication architectures
Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
Pages: 495-498
doi>10.1145/1120725.1120920
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As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not ...
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Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Jae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
Pages: 499-502
doi>10.1145/1120725.1120921
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This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and ...
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Statistical modeling of cross-coupling effects in VLSI interconnects
Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw
Pages: 503-506
doi>10.1145/1120725.1120922
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In this paper, we develop an approach for statistical modeling of crosstalk noise and dynamic delay degradation in coupled RC interconnects under process variations. The proposed model enables closed-form computation of mean and variance of noise peak ...
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Compact and stable modeling of partial inductance and reluctance matrices
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong
Pages: 507-510
doi>10.1145/1120725.1120923
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The sparsification of the reluctance matrix L-1 (where L denotes the usual inductance matrix L) has been widely used in several recent investigations to make the problem of simulation of interconnects tractable. Although ...
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SESSION: High-level synthesis
Fan Mo, Jinian Bian
Scalable interprocedural register allocation for high level synthesis
Rami Beidas, Jianwen Zhu
Pages: 511-516
doi>10.1145/1120725.1120951
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The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the departure from the industrial standard, register transfer level design methodology. Recent ...
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Simultaneous floorplanning and resource binding: a probabilistic approach
Azadeh Davoodi, Ankur Srivastava
Pages: 517-522
doi>10.1145/1120725.1120952
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In this work we present a probabilistic approach to simultaneous floorplanning and resource binding for low power. Traditional approaches iteratively perform floorplanning and resource binding while using crude deterministic wire-length estimates like ...
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Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions
Anup Hosangadi, Farzan Fallah, Ryan Kastner
Pages: 523-528
doi>10.1145/1120725.1120953
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This paper presents a novel technique to reduce the number of operations in Multiplierless implementations of linear DSP transforms, by iteratively eliminating two-term common subexpressions. Our method uses a polynomial transformation of linear systems ...
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A fast algorithm for finding common multiple-vertex dominators in circuit graphs
René Krenz, Elena Dubrova
Pages: 529-532
doi>10.1145/1120725.1120954
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In this paper we present a fast algorithm for computing common multiple-vertex dominators in circuit graphs. Dominators are widely used in CAD applications such as satisfiability checking, equivalence checking, ATPG, technology mapping, decomposition ...
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SESSION: Low power
Hai Zhou, Rob Roy
Low-power domino circuits using NMOS pull-up on off-critical paths
Abdulkadir U. Diril, Yuvraj S. Dhillon, Abhijit Chatterjee, Adit D. Singh
Pages: 533-538
doi>10.1145/1120725.1120956
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Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose a scheme to reduce the power consumption of combinational domino logic blocks ...
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Low-leakage robust SRAM cell design for sub-100nm technologies
Shengqi Yang, Wayne Wolf, Wenping Wang, N. Vijaykrishnan, Yuan Xie
Pages: 539-544
doi>10.1145/1120725.1120957
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A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important ...
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Studying interactions between prefetching and cache line turnoff
Ismail Kadayif, Mahmut Kandemir, Guilin Chen
Pages: 545-548
doi>10.1145/1120725.1120958
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While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance-oriented techniques influence energy behavior of the cache, ...
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The development of high performance FFT IP cores through hybrid low power algorithmic methodology
Wei Han, A. T. Erdogan, T. Arslan, M. Hasan
Pages: 549-552
doi>10.1145/1120725.1120959
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This paper presents a solution based on parallel-pipelined architectures for high throughput and power efficient FFT IP cores. Low power consumption can be gained through the combination of hybrid low power algorithms and architectures. A number of IP ...
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Battery-aware instruction generation for embedded processors
Newton Cheung, Sri Parameswaran, Jörg Henkel
Pages: 553-556
doi>10.1145/1120725.1120960
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Automatic instruction generation is an efficient method to satisfy growing performance and meet design constraints for application specific instruction-set processors. A typical approach for instruction generation is to combine a large group of primitive ...
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A variation-aware low-power coding methodology for tightly coupled buses
Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura
Pages: 557-560
doi>10.1145/1120725.1120961
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This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumption on buses, in which the major sources of the power consumption are the ...
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SESSION: Formal verification: theory and practice
Karem A. Sakallah, Yuan Lu
Automatic assume guarantee analysis for assertion-based formal verification
Dong Wang, Jeremy Levitt
Pages: 561-566
doi>10.1145/1120725.1120963
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Assertion based verification encourages the insertion of many assertions into a design. Typically, not all assertions can be proven (or falsified). The indeterminate assertions require manual analysis in order to determine design correctness -- a time-consuming ...
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TED+: a data structure for microprocessor verification
Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
Pages: 567-572
doi>10.1145/1120725.1120964
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Formal verification of microprocessors requires a mechanism for efficient representation and manipulation of both arithmetic and random Boolean functions. Recently, a new canonical and graph-based representation called TED has been introduced for verification ...
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Improved Boolean function hashing based on multiple-vertex dominators
René Krenz, Elena Dubrova
Pages: 573-578
doi>10.1145/1120725.1120965
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The growing complexity of today's system designs requires fast and robust verification methods. Existing BDD, SAT or ATPG-based techniques do not provide sufficient solutions for many verification instances. Boolean function hashing is a probabilistic ...
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Lower bounds for dynamic BDD reordering
Rüdiger Ebendt, Rolf Drechsler
Pages: 579-582
doi>10.1145/1120725.1120966
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In this paper we present new lower bounds on BDD size. These lower bounds are derived from more general lower bounds that recently were given in the context of exact BDD minimization. The results presented in this paper are twofold: first, we gain deeper ...
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Partitioned model checking from software specifications
Xiushan Feng, Alan J. Hu, Jin Yang
Pages: 583-587
doi>10.1145/1120725.1120967
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With the trends toward higher-level design, verification models written in software, and hardware/software codesign, it is increasingly important to verify that RTL hardware behaves correctly according to an executable software specification. In this ...
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SESSION: Special session
Are we ready for system-level synthesis?
Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe
Pages: 1-1
doi>10.1145/1120725.1120969
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Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.
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SESSION: Robust and low-power clock design
C. K. Cheng, Weiping Shi
Register placement for low power clock network
Yongqiang Lu, C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
Pages: 588-593
doi>10.1145/1120725.1120971
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In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only ...
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Skew scheduling and clock routing for improved tolerance to process variations
Ganesh Venkataraman, C. N. Sze, Jiang Hu
Pages: 594-599
doi>10.1145/1120725.1120972
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The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock tree design algorithm which is driven by the tolerance towards process ...
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Stability analysis of active clock deskewing systems using a control theoretic approach
Vinil Varghese, Tom Chen, Peter Young
Pages: 600-605
doi>10.1145/1120725.1120973
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In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is modelled as a closed loop feedback control system using state space equations. ...
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Process variation robust clock tree routing
Wai-Ching Douglas Lam, Cheng-Kok Koh
Pages: 606-611
doi>10.1145/1120725.1120974
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As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based approach to perform simultaneous non-zero clock skew scheduling and clock ...
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SESSION: DSP
Makoto Ikeda, Xiaoyang Zeng
IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems
Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Jerraya, Pascal Urard
Pages: 612-618
doi>10.1145/1120725.1120976
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The Growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates ...
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A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing
Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera
Pages: 619-622
doi>10.1145/1120725.1120977
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We propose an area-efficient resource-shared VLIW processor (RSVP) for future leaky nm process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way ...
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An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Lingfeng Li, Satoshi Goto, Takeshi Ikenaga
Pages: 623-626
doi>10.1145/1120725.1120978
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In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using ...
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A new register file access architecture for software pipelining in VLIW processors
Yanjun Zhang, Hu he, Yihe Sun
Pages: 627-630
doi>10.1145/1120725.1120979
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This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register ...
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A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Minho Kim, Ingu Hwang, Soo-Ik Chae
Pages: 631-634
doi>10.1145/1120725.1120980
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We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16x16 PE array, an adder tree and ...
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Automatic synthesis and scheduling of multirate DSP algorithms
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan
Pages: 635-638
doi>10.1145/1120725.1120981
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To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of multirate DSP architectures. Whilst others do not trade off area/speed of algorithm ...
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SESSION: Low power and special purpose FPGAs
Lei He, Yu-Liang Wu
A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines
Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay
Pages: 639-644
doi>10.1145/1120725.1120983
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The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State ...
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Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Yan Lin, Fei Li, Lei He
Pages: 645-650
doi>10.1145/1120725.1120984
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Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they consume more power than logic cells. We design area-efficient circuits for ...
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Exploiting temporal idleness to reduce leakage power in programmable architectures
Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
Pages: 651-656
doi>10.1145/1120725.1120985
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One of the biggest challenges that programmable devices like FPGAs are facing in ultra deep sub-micron regime is the exponential rise in leakage power consumption. As technology shrinks below 90nm, a new design paradigm has to evolve to tackle ...
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Methodology for high level estimation of FPGA power consumption
Vijay Degalahal, Tim Tuan
Pages: 657-660
doi>10.1145/1120725.1120986
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Power consumption in FPGA designs calls for power-aware design and power budgeting early in the design cycle. In this work, we leverage the FPGA architecture to present an efficient and accurate methodology for pre-silicon dynamic power estimation of ...
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Leakage control in FPGA routing fabric
Suresh Srinivasan, A. Gayasen, N. Vijaykrishnan, T. Tuan
Pages: 661-664
doi>10.1145/1120725.1120987
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As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the ...
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SESSION: RF circuit design and design methodology
Koichiro Mashiko, Wing Hung Ki
A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion
K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian
Pages: 665-670
doi>10.1145/1120725.1120989
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A design and circuit implementation of a CMOS fourth-order continuous-time bandpass fs/4 sigma delta modulator is presented. The fully differential architecture of the modulator includes integrated LC resonators with active Q enhancement ...
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An elitist distributed particle swarm algorithm for RF IC optimization
Min Chu, David J. Allstot
Pages: 671-674
doi>10.1145/1120725.1120990
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An RF IC optimization methodology based on an elitist distributed particle swarm optimization algorithm is presented. By including a Pareto ranking mechanism and elitism in the algorithm, design alternatives and tradeoff information are provided with ...
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Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization
Min Chu, David J. Allstot
Pages: 675-678
doi>10.1145/1120725.1120991
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A hierarchical divide-and-conquer multi-optimization methodology for phase-locked loop synthesis is presented. By optimizing each building block in the PLL separately with various optimization techniques, high optimization efficiency and good circuit ...
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A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology
Miao Li, Tad Kwasniewski, Shoujun Wang, Yuming Tao
Pages: 679-682
doi>10.1145/1120725.1120992
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A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18μm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the ...
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A dynamic reconfigurable RF circuit architecture
Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu
Pages: 683-686
doi>10.1145/1120725.1120993
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This paper proposes a dynamic reconfigurable architecture for analog RF circuits. The architecture consists of RF circuits and a control circuit. The RF circuits can be reconfigured by bias voltages of transistors and variable passive components, and ...
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Prediction of LC-VCOs' tuning curves with period calculation technique
Zhangwen Tang, Jie He, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min
Pages: 687-690
doi>10.1145/1120725.1120994
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This paper describes a new prediction method of tuning curves of a LC-tank voltage-controlled oscillator (VCO) with period calculation technique. With this period calculation technique, the prediction of oscillator tuning curves is more accurate compared ...
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SESSION: Design techniques in embedded and real-time system
Soon-Hoi Ha, Chenglian Peng
Hardware/software partitioning for platform-based design method
Zhihui Xiong, Jihua Chen, Sikun Li
Pages: 691-696
doi>10.1145/1120725.1120996
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Ant System Algorithm has the advantages of positive feedback and efficient convergence in optimal searching, but it lacks initial pheromone, which greatly limits this algorithm's searching speed. Oriented to Platform-Based Design of System-on-a-Chip, ...
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Abstracting functionality for modular performance analysis of hard real-time systems
Ernesto Wandele, Lothar Thiele
Pages: 697-702
doi>10.1145/1120725.1120997
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System level performance analysis techniques play an important role in the design process of complex embedded systems. They allow to analyze essential characteristics of a system design in an early design stage and support therewith the choice of important ...
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Optimizing intra-task voltage scheduling using data flow analysis
Dongkun Shin, Jihong Kim
Pages: 703-708
doi>10.1145/1120725.1120998
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Intra-task voltage scheduling (IntraDVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In IntraDVS, slack times are estimated by analyzing program's control flow ...
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FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection
John Conner, Yuan Xie, Mahmut Kandemir, Robert Dick, Greg Link
Pages: 709-712
doi>10.1145/1120725.1120999
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Embedded real-time systems are becoming increasingly complex. To combat the rising design cost of those systems, co-synthesis tools that map tasks to systems containing both software and specialized hardware have been developed. As system transient fault ...
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Compiler-directed selective data protection against soft errors
G. Chen, M. Kandemir, M. J. Irwin, G. Memik
Pages: 713-716
doi>10.1145/1120725.1121000
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Soft errors in electronic devices are a growing concern for many embedded systems from diverse domains. Chip vendors are already working with system customers on ways to guard against the effects of soft errors. While error code based protection mechanisms ...
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SESSION: Crosstalk noise avoidance and power/ground network optimization
David Z. Pan, Dennis Sylvester
A perturbation-aware noise convergence methodology for high frequency microprocessors
Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet M. Wang-Roveda
Pages: 717-722
doi>10.1145/1120725.1121002
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We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive ...
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Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
Pages: 723-728
doi>10.1145/1120725.1121003
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An efficient pad assignment algorithm to minimize voltage drop on a power distribution network is proposed. Combination of the successive pad assignment (SPA) and the incremental matrix inversion (IMI) provides an efficient assignment for both location ...
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A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses
Raid Ayoub, Alex Orailoglu
Pages: 729-734
doi>10.1145/1120725.1121004
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In this paper we propose a coding scheme for general-purpose applications that can reduce power dissipation, crosstalk noise and crosstalk delay on the bus lines while simultaneously detecting errors at run time. The reduction in power dissipation can ...
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VLSI on-chip power/ground network optimization considering decap leakage currents
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
Pages: 735-738
doi>10.1145/1120725.1121005
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In today's power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink ...
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Probabilistic congestion model considering shielding for crosstalk reduction
Jinjun Xiong, Lei He
Pages: 739-742
doi>10.1145/1120725.1121006
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We extend an existing probabilistic congestion model to consider shielding for crosstalk reduction. We then develop a multilevel router to study the impact of various congestion models on routing congestion by using large industrial design examples. ...
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SESSION: Others in leading edge designs
Sheldon X.-D. Tan, Hai Zhou
Customized on-chip memories for embedded chip multiprocessors
O. Ozturk, M. Kandemir, G. Chen, M. J. Irwin, M. Karakoy
Pages: 743-748
doi>10.1145/1120725.1121008
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Ensuring that most of data accesses are satisfied from on-chip memories is a critical problem for chip multiprocessors, as the cost of an off-chip access can be very high. Particularly, multiple cores that need to access the off-chip memory system may ...
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Performance driven reliable link design for networks on chips
Rutuparna Ramesh Tamhankar, Srinivasan Murali, Giovanni De Micheli
Pages: 749-754
doi>10.1145/1120725.1121009
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With decreasing feature size of transistors, the interconnect wire delay is becoming a major bottleneck in current Systems on Chips (SoCs). Another effect of shrinking feature size is that the wires are becoming unreliable as they are increasingly ...
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Dynamic power management using on demand paging for networked embedded systems
Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta
Pages: 755-759
doi>10.1145/1120725.1121010
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The power consumption of the network interface plays a major role in determining the total operating lifetime of wireless networked embedded systems. In case of on-demand paging, a low power secondary radio is used to wake up the higher power radio, ...
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An FPGA implementation of low-density parity-check code decoder with multi-rate capability
Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi
Pages: 760-763
doi>10.1145/1120725.1121011
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With superior error correction capability, low-density parity-check (LDPC) has initiated wide scale interests in wireless telecommunication fields. In the past, various structures of single code rate LDPC decoders have been implemented for different ...
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Single-track asynchronous pipeline controller design
Xiao Yong, Zhou Runde
Pages: 764-768
doi>10.1145/1120725.1121012
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Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. It is well known that asynchronous pipeline serves as a powerful method of implementing general computation. This ...
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Using data replication to reduce communication energy on chip multiprocessors
M. Kandemir, G. Chen, F. Li, I. Demirkiran
Pages: 769-772
doi>10.1145/1120725.1121013
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Chip multiprocessors are gaining popularity as they are very suitable for data-intensive embedded and high-end processing. In particular, array-intensive embedded image and video applications can benefit a lot from these architectures due to coarse-grain ...
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SESSION: Synthesis for FPGAs
Kia Bazargan, Evangeline F. Y. Young
Three-dimensional place and route for FPGAs
Cristinel Ababei, Hushrav Mogal, Kia Bazargan
Pages: 773-778
doi>10.1145/1120725.1121015
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We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed ...
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Modern FPGA constrained placement
Wai-Kei Mak
Pages: 779-784
doi>10.1145/1120725.1121016
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We consider the placement of FPGA designs with multiple I/O standards on modern FPGAs that support multiple I/O standards. We propose an efficient approach to solve the constrained I/O placement problem by 0-1 integer linear programming within a high ...
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Clustering techniques for coarse-grained, antifuse FPGAs
Chang Woo Kang, Massoud Pedram
Pages: 785-790
doi>10.1145/1120725.1121017
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In this paper, we present area and performance-driven clustering techniques for coarse-grained, antifuse-based FPGAs. A macro logic cell in this class of FPGAs has multiple inputs and multiple outputs. Starting with this macro cell, a library of small ...
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A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti
Pages: 791-794
doi>10.1145/1120725.1121018
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The main objective of the technique presented in this paper is to exploit the relations between a set of Boolean functions so as to generate one function from another. The paper defines a relation termed as split-equivalence between logical ...
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Resource sharing in pipelined CDFG synthesis
Somsubhra Mondal, Seda Öǧrenci Memik
Pages: 795-798
doi>10.1145/1120725.1121019
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Efficient use of limited available resources on an FPGA remains a crucial problem for synthesizing pipelined designs. Resource sharing addresses this challenge. In this paper, we propose resource sharing techniques that can be incorporated into an automated ...
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SESSION: Analog circuit design
Chris Verhoeven, Junyan Ren
A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator
Hong Zhang, Guican Chen, Ning Li
Pages: 799-802
doi>10.1145/1120725.1121021
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This paper presents a voltage-controlled oscillator (VCO) with high linearity in frequency tuning. The VCO has two control inputs. One controls a pair of p+/n-well varactors to realize continuous tuning and the other controls a pair of MOS ...
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Adiabatic CMOS gate and adiabatic circuit design for low-power applications
Guoqiang Hang
Pages: 803-808
doi>10.1145/1120725.1121022
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The methodology for designing adiabatic circuits employing two-phase power clock, is investigated. First, algebraic expressions for and properties of power-clocked signals are discussed. Then the design of adiabatic gates based on AC power supply and ...
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An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system
Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta
Pages: 809-814
doi>10.1145/1120725.1121023
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This paper describes an automated device sizing system for current-steering D/A converters (DACs) and an 11-bit 160-MS/s DAC implemented using this system. Based on an analysis of harmonic distortion (or spurious) of the DAC, a circuit technique named ...
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A class D audio power amplifier with high-efficiency and low-distortion
Chen Hai, Wu Xiaobo
Pages: 815-818
doi>10.1145/1120725.1121024
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Efficiency and fidelity is of key importance to audio power amplifiers. A new configuration of power amplifier was proposed to improve both of them. By combining a linear amplifier with a nonlinear one in parallel, it features high efficiency and low ...
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Substrate noise modeling in early floorplanning of MS-SOCs
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang
Pages: 819-823
doi>10.1145/1120725.1121025
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We propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of Mixed-Signal System-on-Chips (MS-SOCs). We assume no precise layout information about IP cores ...
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SESSION: Low power design for embedded and real-time systems
Joerg Henkel, Jihua Chen
Instruction scheduling of VLIW architectures for balanced power consumption
Shu Xiao, Edmund M-K. Lai
Pages: 824-829
doi>10.1145/1120725.1121027
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An instruction word in VLIW (very long instruction word) processors consists of a variable number of individual instructions. Therefore the power consumption variation over time significantly depends on the parallel instruction schedule generated by ...
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Power minimization techniques on distributed real-time systems by global and local slack management
Shaoxiong Hua, Gang Qu
Pages: 830-835
doi>10.1145/1120725.1121028
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Recently, a static power management with parallelism (P-SPM) technique has been proposed to reduce the energy consumption of distributed systems to execute a set of real-time dependent tasks [7]. The authors claimed that the proposed P-SPM outperforms ...
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A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors
Jaewon Seo, Nikil D. Dutt
Pages: 836-841
doi>10.1145/1120725.1121029
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Dynamic voltage scaling (DVS) which is an effective energy minimization technique has been well-studied in recent years. Yet the problem of selecting voltage levels for multiple voltage DVS systems remains an unresolved issue. In this paper, we present ...
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A dynamic voltage scaling algorithm for energy reduction in hard real-time systems
Van R. Culver, Sunil P. Khatri
Pages: 842-845
doi>10.1145/1120725.1121030
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As the quantity and functional complexity of battery powered portable devices continues to rise, energy efficient design of such devices has become increasingly important. Many real-time scheduling algorithms have been developed recently to reduce energy ...
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An efficient dynamic task scheduling algorithm for battery powered DVS systems
Jianli Zhuo, Chaitali Chakrabarti
Pages: 846-849
doi>10.1145/1120725.1121031
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Battery lifetime enhancement is a critical design parameter for mobile computing devices. Maximizing battery life-time is a particularly difficult problem due to the non-linearity of the battery behavior and its dependence on the characteristics of the ...
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SESSION: Synthesis for low power
Shih-Chieh Chang, Farzan Falla
Optimal module and voltage assignment for low-power
Deming Chen, Jason Cong, Junjuan Xu
Pages: 850-855
doi>10.1145/1120725.1121054
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Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow ...
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Bitwidth-aware scheduling and binding in high-level synthesis
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
Pages: 856-861
doi>10.1145/1120725.1121055
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Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifications without bitwidth analysis may introduce wasted resources. Furthermore, ...
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Functionality directed clustering for low power MTCMOS design
Tsuang-Wei Chang, Ting-Ting Hwang, Sheng-Yu Hsu
Pages: 862-867
doi>10.1145/1120725.1121056
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Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when MTCMOS circuit is designed. If the sleep transistor size is too large, the circuit performance can be ...
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Wake-up protocols for controlling current surges in MTCMOS-based technology
Azadeh Davoodi, Ankur Srivastava
Pages: 868-871
doi>10.1145/1120725.1121057
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This paper proposes strategies to control the wake-up noise for circuits implemented in MTCMOS technology. In MTCMOS circuits, during the switchings between the active and standby modes, sudden surges in current happens due to floating voltages at the ...
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On multiple-voltage high-level synthesis using algorithmic transformations
Hsueh-Chih Yang, Lan-Rong Dung
Pages: 872-876
doi>10.1145/1120725.1121058
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This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise ...
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SESSION: New circuit and methodology
Jinmei Lai, Zheng Shi
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin
Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim
Pages: 877-882
doi>10.1145/1120725.1121060
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This paper proposes the bit-line clamping scheme for a stable signal margin in Magnetoresistance RAM. MRAM distinguishes data by the difference of resistance in MTJ. However, there are so many error sources in MTJ that it limits a yield factor. In this ...
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Constructing zero-deficiency parallel prefix adder of minimum depth
Haikun Zhu, Chung-Kuan Cheng, Ronald Graham
Pages: 883-888
doi>10.1145/1120725.1121061
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Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as SC(n) and dC(n) respectively. ...
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An accurate 1.08-GHz CMOS LC voltage-controlled oscillator
Zhangwen Tang, Jie He, Hongyan Jian, Hao Min
Pages: 889-892
doi>10.1145/1120725.1121062
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An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the frequency ...
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Area-IO DRAM/logic integration with system-in-a-package (SiP)
Anru Wang, Wayne Dai
Pages: 893-896
doi>10.1145/1120725.1121063
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This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (Chip-Laminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can achieve ...
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Design of an efficient memory subsystem for network processor
Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li
Pages: 897-900
doi>10.1145/1120725.1121064
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The rapid growth of backbone network traffic increases the gaps among the available network bandwidth, the CPU computation power and the memory bandwidth. The memory bandwidth has become the main performance bottleneck of network processor. In this paper, ...
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Design of clocked circuits using UML
Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh Kumar Pilakkat
Pages: 901-904
doi>10.1145/1120725.1121065
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Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unified Modeling Language (UML) has been proposed as design tool in real time ...
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SESSION: FPGA circuits and architectures
Wai-Kei Mak, Feng Zhou
A function generator-based reconfigurable system
Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti
Pages: 905-909
doi>10.1145/1120725.1121067
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This paper proposes a new reconfigurable system which has a function generator-based CLB architecture. This is different from the standard look-up table (LUT) based CLB architectures available in commercial FPGAs. The new function generation architecture ...
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Crossbar based design schemes for switch boxes and programmable interconnection networks
Hongbing Fan, Yu-Liang Wu
Pages: 910-915
doi>10.1145/1120725.1121068
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Crossbars have been considered one of the most standard switching modules in conventional communication networks due to its simplicity in routing algorithm and fabrication regularity. While in programmable on-chip interconnection networks such as the ...
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A domain specific reconfigurable Viterbi fabric for system-on-chip applications
Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay
Pages: 916-919
doi>10.1145/1120725.1121069
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A novel embedded dynamically reconfigurable fabric for implementing the Viterbi algorithm in a System-on-Chip device is presented in this paper. The proposed reconfigurable fabric can support Viterbi implementations for different standards, such as GSM, ...
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Design of a high performance FFT processor based on FPGA
Chu Chao, Zhang Qin, Xie Yingke, Han Chengde
Pages: 920-923
doi>10.1145/1120725.1121070
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The design method of a real-time FFT processor is presented. By optimizing algorithm of memory mapping and generation of twiddle factors, a radix-4 butterfly can be calculated in one clock cycle. An approach to adaptive overflow control is also introduced ...
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Increasing FPGA resilience against soft errors using task duplication
G. Chen, F. Li, M. Kandemir, I. Demirkiran
Pages: 924-927
doi>10.1145/1120725.1121071
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Reconfigurable computing systems are becoming increasingly widespread as they bring the flexibility of programmable systems and approach the performance of ASICs. While the prior research on FPGAs mainly studied issues such as performance, power, and ...
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Automatic extraction of function bodies from software binaries
Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee
Pages: 928-931
doi>10.1145/1120725.1121072
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This paper describes a method for automatically extracting function bodies from linked software binaries. It utilizes procedure-calling conventions along with limited control and data flow information. It has been tested with the TI C6000 DSP processor ...
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SESSION: (Special session) EDA market in China
Panel III: EDA market in China
David Chen, Nancy Wu, Wayne Dai, Jun Tan, Weiping Liu, Hao Min, Jian-yue Pan
Pages: 1-1
doi>10.1145/1120725.1121074
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SESSION: Poster session I
Modeling SystemC design in UML and automatic code generation
Chen Xi, Lu JianHua, Zhou ZuCheng, Shang YaoHui
Pages: 932-935
doi>10.1145/1120725.1120760
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The combination of Unified Modeling Language (UML) and SystemC has led to an object-oriented high-level design automation methodology. In this paper, a novel bi-directional UML-SystemC translation tool UMLSC is proposed. Specifically, a set of ...
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Enabling RTOS simulation modeling in a system level design language
M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Pages: 936-939
doi>10.1145/1120725.1120761
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In this paper, we propose a new process definition (T-THREAD) and an extension to the existing SystemC simulation engine (SIM_API library) to capture the real time aspects of RTOS simulation models in an SLDL like SystemC. We describe the execution semantics ...
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A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Pages: 940-943
doi>10.1145/1120725.1120762
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Architectures based on Very Long Instruction Word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and ...
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Multi-metric and multi-entity characterization of applications for early system design exploration
Lukai Cai, Andreas Gerstlauer, Daniel Gajski
Pages: 944-947
doi>10.1145/1120725.1120763
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At system level, intensively analyzing the system application will produce a variety of useful characteristics and provide designers valuable exploration indications. In this paper, we present such an analysis approach based on the instrumentation-based ...
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An integrated performance and power model for superscalar processor designs
Yongxin Zhu, Weng-Fai Wong, Ştefan Andrei
Pages: 948-951
doi>10.1145/1120725.1120764
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On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints. This paper describes an integrated performance and power analytical ...
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Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms
Zhe Ma, Francky Catthoor, Johan Vounckx
Pages: 952-955
doi>10.1145/1120725.1120765
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Nowadays, the System-on-a-chip (SoC) has integrated more processors onto a single chip. Applications are also consisting of multiple (sub)tasks that are presented as different source code which can be partly executed concurrently. However, the subtask-level ...
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A flexible framework for communication evaluation in SoC design
Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
Pages: 956-959
doi>10.1145/1120725.1120766
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We present SoCExplore, a framework for fast communication-centric design space exploration of complex SoCs with network-based interconnects. Speed-up in exploration is achieved through abstraction of computation as a high-level trace, and accuracy is ...
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Feasibility analysis of messages for on-chip networks using wormhole routing
Zhonghai Lu, Axel Jantsch, Ingo Sander
Pages: 960-964
doi>10.1145/1120725.1120767
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The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing properties. We present a novel feasibility analysis for real-time (RT) and nonreal-time ...
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A clustering technique to optimize hardware/software synchronization
Junyu Peng, Samar Abdi, Daniel Gajski
Pages: 965-968
doi>10.1145/1120725.1120768
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In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flow of the specification. Since traffic between components is expensive, our ...
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Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed A. Jerraya
Pages: 969-972
doi>10.1145/1120725.1120769
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Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC ...
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On combining iteration space tiling with data space tiling for scratch-pad memory systems
Chunhui Zhang, Fadi Kurdahi
Pages: 973-976
doi>10.1145/1120725.1120770
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Most previous studies on tiling concentrate on iteration space only for cache-based memory systems. However, more and more real-time embedded systems are adopting Scratch-Pad Memories (SPMs) which emphasize on the management of data flow through data-oriented ...
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REMIC: design of a reactive embedded microprocessor core
Zoran Salcic, Dong Hui, Partha Roop, Morteza Biglari-Abhari
Pages: 977-981
doi>10.1145/1120725.1120771
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Reactivity on external events is an important feature of almost all embedded systems. In this paper we present the design of a new, reactive embedded microprocessor called REMIC, that supports reactivity in a new way following the paradigm of synchronous ...
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Online hardware/software partitioning in networked embedded systems
Thilo Streichert, Christian Haubelt, Jürgen Teich
Pages: 982-985
doi>10.1145/1120725.1120772
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Today's embedded systems are typically distributed and more often confronted with time-varying demands. Existing methodologies that optimize the partitioning of computational tasks to hardware (HW) and software (SW) at compile-time become obsolete ...
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Comparing high-level modeling approaches for embedded system design
Lisane Brisolara, Leandro Becker, Luigi Carro, Flávio Wagner, Carlos E. Pereira, Ricardo Reis
Pages: 986-989
doi>10.1145/1120725.1120773
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This paper present a comparison between three different high-level modeling approaches for embedded systems design, focusing on systems that require dataflow models. The proposed evaluation investigates the facilities provided by these approaches for ...
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Deriving a new efficient algorithm for min-period retiming
Hai Zhou
Pages: 990-993
doi>10.1145/1120725.1120774
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A new efficient algorithm is derived for the minimal period retiming problem by formal methods. Contrary to all previous algorithms, which used binary search to check feasibilities on a range of candidate periods, the derived algorithm checks the optimality ...
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K-disjointness paradigm with application to symmetry detection for incompletely specified functions
Kuo-Hua Wang, Jia-Hung Chen
Pages: 994-997
doi>10.1145/1120725.1120775
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In this paper, we propose a K-disjointness paradigm that can effectively search all pairs of minterms with Hamming distance K between two Boolean functions. By this paradigm, we correlate it with symmetry detection problem and propose an efficient symmetry ...
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Logic optimization using rule-based randomized search
Petra Färm, Elena Dubrova, Andreas Kuehlmann
Pages: 998-1001
doi>10.1145/1120725.1120776
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In this paper we describe a new logic synthesis approach based on rule-based randomized search using simulated annealing. Our work is motivated by two observations: (1) Traditional logic synthesis applies literal count as the primary quality metric during ...
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Fast synthesis of exact minimal reversible circuits using group theory
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski
Pages: 1002-1005
doi>10.1145/1120725.1120777
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We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory problems, we use the powerful algebraic software GAP to solve such problems. ...
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Design and design automation of rectification logic for engineering change
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone
Pages: 1006-1009
doi>10.1145/1120725.1120778
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In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addition to meet the design schedule for the new implementation, the reduction ...
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Power minimization for dynamic PLAs
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
Pages: 1010-1013
doi>10.1145/1120725.1120779
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In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. ...
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Integrated algorithmic logical and physical design of integer multiplier
Shuo Zhou, Bo Yao, Jian-Hua Liu, Chung-Kuan Cheng
Pages: 1014-1017
doi>10.1145/1120725.1120780
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This paper presents an integrated methodology for high-performance integer multiplier design, which combines algorithmic partial product generation, logic synthesis, and physical layout into a unified process. The interconnect delay, which dominates ...
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Arrival time aware scheduling to minimize clock cycle length
R. Ruiz-Sautua, M. C. Molina, J. M. Mendías, R. Hermida
Pages: 1018-1021
doi>10.1145/1120725.1120781
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Conventional scheduling algorithms usually adjust the clock cycle duration to the execution time of the longest operations. This results in large slack times wasted in those cycles with faster operations. To reduce the wasted times multi-cycle and chaining ...
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Efficient synthesis of speed-independent combinational logic circuits
W. B. Toms, D. A. Edwards
Pages: 1022-1026
doi>10.1145/1120725.1120782
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Speed-Independent synthesis of combinational logic datapath circuits using tools such as Petrify is often inefficient or infeasible because such circuits typically contain many concurrent inputs and independent outputs. This paper presents a practical ...
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A practical cut-based physical retiming algorithm for field programmable gate arrays
Peter Suaris, Dongsheng Wang, Nan-Chi Chou
Pages: 1027-1030
doi>10.1145/1120725.1120783
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This paper presents a heuristic cut-based retiming algorithm for FPGA designs. It handles complex retiming constraints including timing, architectural and structural constraints; improves retimeability by incorporating logic resynthesis; and efficiently ...
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BDD-based two variable sharing extraction
Dennis Wu, Jianwen Zhu
Pages: 1031-1034
doi>10.1145/1120725.1120784
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It has been shown that Binary Decision Diagram (BDD) based logic synthesis enjoys faster runtime than the classic logic synthesis systems based on Sum of Product (SOP) form. However, its synthesis quality has not been on par with the classic method due ...
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SESSION: Poster session II
Supporting sequential assumptions in hybrid verification
Ed Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Tony Ma
Pages: 1035-1038
doi>10.1145/1120725.1120818
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We present a method for using a set of temporal properties (SVA, PSL, OVA, RTL monitors) as environment models for industrial-strength hybrid verification that combines formal methods with constrained random simulation. We demonstrate the effectiveness ...
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Automatic functional test program generation for microprocessor verification
Tun Li, Dan Zhu, Lei Liang, Yang Guo, SiKun Li
Pages: 1039-1042
doi>10.1145/1120725.1120819
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A novel specification driven and constraints solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. Our microprocessor architectural automatic test program generator ...
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Forward symbolic model checking for real time systems
Georgios Logothetis
Pages: 1043-1046
doi>10.1145/1120725.1120820
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Synchronous languages are widely used in industrial applications for the design and implementation of real-time embedded and reactive systems and are also well-suited for real-time verification purposes, since they have clean formal semantics. In this ...
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Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice
Yinlei Yu, Sharad Malik
Pages: 1047-1051
doi>10.1145/1120725.1120821
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Despite the increasing use of QBF solvers, current QBF solvers do not provide for any mechanism to verify their results. This paper demonstrates a methodology for independently validating the results of a DLL based QBF solver using the traces generated ...
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Priority directed test generation for functional verification using neural networks
Hao Shen, Yuzhuo Fu
Pages: 1052-1055
doi>10.1145/1120725.1120822
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Functional verification is the bottleneck in delivering today's highly integrated electronic systems and chips. We should notice the simulation times and computation resource challenge in the automatic pseudo-random test generation and a novel solution ...
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Comparison of schemes for encoding unobservability in translation to SAT
Miroslav N. Velev
Pages: 1056-1059
doi>10.1145/1120725.1120823
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Compared are seven schemes for encoding unobservability of logic blocks in Boolean-to-CNF translation. Four of the schemes are based on merging of logic blocks with adjacent gates toward the primary output. Two are based on using CNF unobservability ...
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Implication of assertion graphs in GSTE
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song
Pages: 1060-1063
doi>10.1145/1120725.1120824
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We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal verification of digital systems. Assertion graphs are used for property and ...
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XTW, a parallel and distributed logic simulator
Qing XU, Carl Tropper
Pages: 1064-1069
doi>10.1145/1120725.1120825
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In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic logic simulation. We incorporate both of these techniques in a simulator XTW. XTW groups LPs into clusters, and makes use ...
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Comprehensive frequency dependent interconnect extraction and evaluation methodology
Rong Jiang, Charlie Chung-Ping Chen
Pages: 1070-1073
doi>10.1145/1120725.1120826
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This paper presents a wide frequency range interconnect extraction and analysis methodology. First, an improved reluctance-based extraction algorithm is proposed to generate compact interconnect models at some sample frequencies. Then, DLSCF (Discrete ...
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On-chip thermal gradient analysis and temperature flattening for SoC design
Takashi Sato, Junji Ichimiya, Nobuto Ono, Kotaro Hachiya, Masanori Hashimoto
Pages: 1074-1077
doi>10.1145/1120725.1120827
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This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic, power density, and floorplan on thermal gradient and clock skew ...
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Return path selection for loop RL extraction
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
Pages: 1078-1081
doi>10.1145/1120725.1120828
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This paper propose a systematic method to select power/ground wires that should be considered in interconnect RL extraction. The return current distribution affects loop characteristic of interconnects. To extract exact RL value, all of return paths ...
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Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects
Natalie Nakhla, Ram Achar, Michel Nakhla, Anestis Dounavis
Pages: 1082-1085
doi>10.1145/1120725.1120829
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Time-domain macromodeling of high speed interconnects characterized by distributed transmission lines has generated immense interest during the recent years. It has been demonstrated that, preserving passivity of the macromodel is essential to guarantee ...
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Vector extraction for average total power estimation
Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li
Pages: 1086-1089
doi>10.1145/1120725.1120830
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Power consumption has become a primary constraint of integrated circuit design. Many models have been proposed to evaluate dynamic and leakage power in every design level. However, how to accurately predict TPower, the total power with dynamic and leakage ...
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Relaxed hierarchical power/ground grid analysis
Yici Cai, Zhu Pan, Shelton X-D Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
Pages: 1090-1093
doi>10.1145/1120725.1120831
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This paper proposes a novel hierarchical approach to the efficient analysis of large VLSI power/ground grids. Different from the existing hierarchical approach where sub-circuit equivalent models are sparsified with computation-intensive integer programming ...
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Sleep transistor sizing using timing criticality and temporal currents
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
Pages: 1094-1097
doi>10.1145/1120725.1120832
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Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to gate the power supply. This paper presents a new methodology based on timing ...
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Timing analysis considering temporal supply voltage fluctuation
Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
Pages: 1098-1101
doi>10.1145/1120725.1120833
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This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with an equivalent power/ground voltage. This replacement reduces complexity that comes from ...
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Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity
G Peter Fang, David C Yeh, David Zweidinger, Lawrence A Arledge, Vinod Gupta
Pages: 1102-1106
doi>10.1145/1120725.1120834
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In this work, we developed a highly memory-efficient, accurate table model that is 10X+ faster than its analytical counterparts: BSIN3/4 models. Speed derives from linear interpolation; accuracy and memory efficiency result from the unstructured grid ...
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Congestion prediction in floorplanning
Chiu-wing Sham, Evangeline F. Y. Young
Pages: 1107-1110
doi>10.1145/1120725.1120835
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Routability optimization has become the major concern in floorplanning. In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, interconnect has become a dominant factor to the overall performance ...
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CMP aware shuttle mask floorplanning
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
Pages: 1111-1114
doi>10.1145/1120725.1120836
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By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the rising mask cost. A challenging floorplanning problem is to optimally pack ...
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An improved P-admissible floorplan representation based on Corner Block List
Renshen Wang, Sheqin Dong, Xianlong Hong
Pages: 1115-1118
doi>10.1145/1120725.1120837
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The Corner Block List representation (CBL) introduced in 2000 is an efficient and effective model for floorplanning and placement while still having some limitations such as redundancy and incompleteness. In this paper, we present an auxiliary 3-Route ...
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Fast floorplanning by look-ahead enabled recursive bipartitioning
Jason Cong, Michail Romesis, Joseph R. Shinnerl
Pages: 1119-1122
doi>10.1145/1120725.1120838
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A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by ...
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LFF algorithm for heterogeneous FPGA floorplanning
Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu
Pages: 1123-1126
doi>10.1145/1120725.1120839
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With increasing of FPGA densities and greater demand for performance, a hierarchical approach is often used in FPGA design. Floorplanning is a key ingredient of the hierarchical approaches. However, heterogeneous resources across FPGA fabric have made ...
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Placement for configurable dataflow architecture
Mongkol Ekpanyapong, Michael Healy, Sung Kyu Lim
Pages: 1127-1130
doi>10.1145/1120725.1120840
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As wire delay increasingly becomes a significant performance bottleneck in monolithic architectures, there is a strong motivation to move to Dataflow Architectures. In this paper, we propose a set of placement algorithms for generic dataflow architectures. ...
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Wire congestion and thermal aware 3D global placement
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim
Pages: 1131-1134
doi>10.1145/1120725.1120841
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The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we ...
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Placement with symmetry constraints for analog layout design using TCG-S
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang
Pages: 1135-1137
doi>10.1145/1120725.1120842
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In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module placement with symmetry constraints for analog design using the Transitive ...
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SESSION: Poster session III
An LP-based methodology for improved timing-driven placement
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal
Pages: 1139-1143
doi>10.1145/1120725.1120925
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A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, ...
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Placement stability metrics
Chuck J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet C. YILDIZ
Pages: 1144-1147
doi>10.1145/1120725.1120926
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To achieve timing closure, one often has to run through several iterations of physical synthesis flows, for which placement is a critical step. During these iterations, one hopes to consistently move towards design convergence. A placement algorithm ...
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Redundant-via enhanced maze routing for yield improvement
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
Pages: 1148-1151
doi>10.1145/1120725.1120927
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Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm ...
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Interconnect estimation without packing via ACG floorplans
Jia Wang, Hai Zhou
Pages: 1152-1155
doi>10.1145/1120725.1120928
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ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between ...
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Timing driven track routing considering coupling capacitance
Di Wu, Jiang Hu, Min Zhao, Rabi Mahapatra
Pages: 1156-1159
doi>10.1145/1120725.1120929
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As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven routing. In this paper, a coupling aware timing driven track routing heuristic is proposed. ...
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Multilevel full-chip gridless routing considering optical proximity correction
Tai-Chen Chen, Yao-Wen Chang
Pages: 1160-1163
doi>10.1145/1120725.1120930
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To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great flexibility. The gridless routing is much more difficult than the grid-based ...
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Improving the scalability of SAMBA bus architecture
Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
Pages: 1164-1167
doi>10.1145/1120725.1120931
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SAMBA bus [1] is a high performance bus architecture that can deliver multiple transactions in one bus cycle under single-winner bus arbitration. The bus architecture displays several advantages such as, high bandwidth, low latency, and low performance ...
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Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling
Jeng-Liang Tsai, Charlie Chung-Ping Chen
Pages: 1168-1171
doi>10.1145/1120725.1120932
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Zero-skew clock-tree with minimum clock-delay is preferable due to its low unintentional and process-variation induced skews. We propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout ...
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Register-transfer level functional scan for hierarchical designs
Ho Fai Ko, Qiang Xu, Nicola Nicolici
Pages: 1172-1175
doi>10.1145/1120725.1120933
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This paper discusses the potential benefits of inserting scan chains (SCs) in hierarchical designs at the register-transfer level (RTL) of design abstraction. Using new algorithms for functional scan chain design, it is shown how tight timing constraints ...
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Using fault model relaxation to diagnose real scan chain defects
Yu Huang, Wu-Tung Cheng, Greg Crowell
Pages: 1176-1179
doi>10.1145/1120725.1120934
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Software-based scan chain fault diagnosis is typically composed of two steps. First, scan chain flush patterns are used to identify faulty chains and fault models. This is followed by chain diagnosis using scan patterns in the second step. In this paper, ...
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A retention-aware test power model for embedded SRAM
Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov
Pages: 1180-1183
doi>10.1145/1120725.1120935
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This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant ...
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On-chip accumulated jitter measurement for phase-locked loops
Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang
Pages: 1184-1187
doi>10.1145/1120725.1120936
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A time-to-digital Converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated ...
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SoC test scheduling using the B-tree based floorplanning technique
Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang
Pages: 1188-1191
doi>10.1145/1120725.1120937
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We present in this paper a new algorithm to co-optimize the problems of test scheduling and core wrapper design under power constraints for core-based SoC (System on Chip) designs. The problem of test scheduling is first transformed into a floorplanning ...
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Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands
Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu
Pages: 1192-1195
doi>10.1145/1120725.1120938
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Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time ...
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Efficiently generating test vectors with state pruning
Ying Chen, Dennis Abts, David J. Lilja
Pages: 1196-1199
doi>10.1145/1120725.1120939
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This paper extends the depth first search (DFS) used in the previously proposed witness string method for generating efficient test vectors. A state pruning method is added that exploits different search heuristics in simultaneous searches. Using an ...
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Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs
E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan
Pages: 1200-1203
doi>10.1145/1120725.1120940
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This paper proposes a cluster-based parity-checking technique that can detect 100% of all Single Event Upset (SEU) faults in the LUTs of SRAM-based FPGAs. The paper describes two different Configurable Logic Block (CLB) architectures that could be used ...
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Comprehensive analysis and optimization of CMOS LNA noise performance
Dong Feng, Bingxue Shi
Pages: 1204-1207
doi>10.1145/1120725.1120941
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Comprehensive analysis of CMOS low noise amplifier (LNA) noise performance is presented in this paper, including channel noise and induced gate noise in MOS devices. The impacts of distributed gate resistance and intrinsic channel resistance on noise ...
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An analog front-end IP for 13.56MHz RFID interrogators
Jung-Hyun Cho, Suk-Byung Chai, Chung-Gi Song, Kyung-Won Min, Shiho Kim
Pages: 1208-1211
doi>10.1145/1120725.1120942
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An analog front-end circuit for 13.56MHz RFID interrogators compatible with ISO14443, ISO15693 and ISO18000-3 Mode 1 RFID interrogators was designed and fabricated by using 0.35μm double poly CMOS process. The fabricated chip was operated at 3.3 volt ...
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A two-stage genetic algorithm method for optimization the ΣΔ modulators
A. Zahabi, O. Shoaei, Y. Koolivand, P. Jabehdar-maralani
Pages: 1212-1215
doi>10.1145/1120725.1120943
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A two-stage optimization approach for the design of ΣΔ Modulators using Genetic Algorithm has been proposed. The conversion speed and consumed CPU time of the design process have been reduced significantly by utilizing the combination of ...
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A novel differential VCO circuit design for USB Hub
Gong Qian, Yuan Guo-shun
Pages: 1216-1219
doi>10.1145/1120725.1120944
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The paper describes a novel differential Voltage Controlled Oscillator circuit, which is used in the phase locked loop of a USB hub chip. The output clock signals can be altered from 36MHz to 96MHz by changing the value of control signals. The Voltage ...
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Static power minimization in current-mode circuits
M. S. Bhat, H. S. Jamadagni
Pages: 1220-1223
doi>10.1145/1120725.1120945
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We propose a method involving selective signal gating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in ...
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A novel transmitter for 1000Base-T physical transceiver
Pages: 1224-1227
doi>10.1145/1120725.1120946
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This paper describes a transmitter used in 1000Base-T PHY chip. A Digital-to-Analog Converter with 5bit resolution, 8bit accuracy, 125MHz sample rate and 4ns transition timing has been implemented to satisfy all the specifications of the Gigabit Ethernet ...
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A novel data processing circuit in high-speed serial communication
Yongjian Tang, Lenian He, Xiaolang Yan
Pages: 1228-1231
doi>10.1145/1120725.1120947
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A novel data processing circuit in high-speed serial communication has been demonstrated in this work. The circuit, including a serializer and a frequency divider, was developed to convert the transmission signals into the desired format. The chip design ...
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A monolithic CMOS L band DAB receiver
Ziqiang Wang, Baoyong Chi, Min Lin, Shuguang Han, Lu Liu, Jinke Yao, Zhihua Wang
Pages: 1232-1235
doi>10.1145/1120725.1120948
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This paper presents a fully integrated CMOS low-IF receiver working at L-band for DAB application. An image-rejection low noise amplifier (LNA) supplies over 30dB image rejection in the whole band. A calibration circuit improves matching of quadrature ...
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A bipolar IF amplifier/RSSI for ASK receiver
Yonggang Tao, Yongsheng Xu, Wei Jin, Hui Yu, Zongsheng Lai
Pages: 1236-1239
doi>10.1145/1120725.1120949
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A bipolar logarithmic intermediate-frequency (IF) amplifier with received signal strength indicator (RSSI) circuit for ASK Receiver is presented. The amplifier realizes a piecewise approximation to an exact logarithmic response. In the demodulating Log ...
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SESSION: Poster session IV
Evaluation of dual VDD fabrics for low power FPGAs
Rajarshi Mukherjee, Seda Ogrenci Memik
Pages: 1240-1243
doi>10.1145/1120725.1121033
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Power efficiency is becoming an increasingly important design aspect for FPGAs. Recently it has been shown that well-known power minimization techniques in the ASICs such as creating supply voltage (Vdd) scalable islands of different granularity ...
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Design of an application-specific PLD architecture
Jae-Jin Lee, Gi-Yong Song
Pages: 1244-1247
doi>10.1145/1120725.1121034
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This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. ...
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Event-oriented computing with reconfigurable platform
Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita
Pages: 1248-1251
doi>10.1145/1120725.1121035
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Recently, reconfigurable computing has come under the spotlight as the new computing paradigm. A machine employing this paradigm combines the flexibility of a general purpose processor with the performance of a dedicated system. In this paper, we propose ...
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Reconfigurable adaptive FEC system with interleaving
Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
Pages: 1252-1255
doi>10.1145/1120725.1121036
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This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units ...
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An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay
Pages: 1256-1259
doi>10.1145/1120725.1121037
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We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA High-Speed Bus (AHB). The architecture features multiple low-area flyby DMA blocks for transferring configuration data. Furthermore, the architecture eliminates ...
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Using GALS architecture to reduce the impact of long wire delay on FPGA performance
Xin Jia, Ranga Vemuri
Pages: 1260-1263
doi>10.1145/1120725.1121038
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Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. Globally Asynchronous Locally Synchronous (GALS) design is considered a potential solution to this issue. An important design decision ...
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A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Tiejun Li, Sikun Li, Chengdong Shen
Pages: 1264-1267
doi>10.1145/1120725.1121039
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This paper proposes a flexible, efficient and configurable motion estimation architecture. The core of this architecture is a motion estimation engine NPSPE (Nine Points Search Pattern Engine), which can support the latest efficient block-based motion ...
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A fast digit-serial systolic multiplier for finite field GF(2m)
Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong
Pages: 1268-1271
doi>10.1145/1120725.1121040
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This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every [m/D] ...
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Adaptive fuzzy control scheduling of window-constrained real-time systems
Zhu Xiangbin, Tu ShiLiang
Pages: 1272-1275
doi>10.1145/1120725.1121041
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DWCS (Dynamic window-constrained scheduling) algorithm has good performance when the DWCS scheduler is not overloaded. But when the scheduler is overloaded, many violations will be produced and they are not uniformly distributed. In this paper, we present ...
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A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder
Bo Shen, Junhua Tian, Zheng Li, Jianing Su, Qianling Zhang
Pages: 1276-1279
doi>10.1145/1120725.1121042
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A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4~256QAM with variable bit rate up to 80Mbps. It integrates a 10-bit 40MSPS ADC, (204,188) Reed-Solomon decoder ...
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Partitioned bus coding for energy reduction
Lin Xie, Peiliang Qiu, Qinru Qiu
Pages: 1280-1283
doi>10.1145/1120725.1121043
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For VLSI design in deep submicron technology, the bus energy reduction has become more and more important. This paper studies the bus partition scheme for the Transition Pattern Coding (TPC). The genetic algorithm based approach is used. A closed-form ...
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An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000
Yanju Han, Chao Xu, Yizhen Zhang
Pages: 1284-1287
doi>10.1145/1120725.1121044
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Embedded block coding with optimized truncation (EBCOT) is a critical part in JPEG2000 systems. There are bit-plane and pass dual parallel methods that can speed up the encoding, but the acceleration is always companied with the complication of the circuit ...
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A generalized quadrature bandpass sampling in radio receivers
Yi-Ran Sun, Svante Signell
Pages: 1288-1291
doi>10.1145/1120725.1121045
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Bandpass Sampling (BPS) realizes frequency down-conversion by undersampling. Noise aliasing as the direct consequence of the lower sampling rate causes a performance degradation. In this paper, a Generalized Quadrature BPS (GQBPS) combined with a filter ...
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Reducing leakage power in instruction cache using WDC for embedded processors
Xin Lu, Yuzhuo Fu
Pages: 1292-1295
doi>10.1145/1120725.1121046
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Power consumption is an important design issue of current embedded systems and SoC. It has been shown that instruction cache accounts for a significant portion of the power dissipation of the whole processor chip. WDC (Way-Decay Cache) proposed in this ...
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System-level architectural exploration using allocation-on-demand technique
Qiang Wu, Jinian Bian, Hongxi Xue
Pages: 1296-1298
doi>10.1145/1120725.1121047
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Architectural exploration is very important in embedded system design and SoC design. In this paper, a new heuristic algorithm using the allocation-on-demand technique is proposed to solve this problem. Unlike previous research efforts, this algorithm ...
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A fractional delay-locked loop for on chip clock generation applications
P. Torkzadeh, A. Tajalli, M. Atarodi
Pages: 1300-1309
doi>10.1145/1120725.1121048
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A fractional multiplying delay-locked loop (FMDLL) for high speed on-chip clock generation applications is presented. The proposed DLL architecture overcomes some drawbacks of phase-locked loops (PLLs) such as jitter accumulation and stability while ...
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A novel O(n) parallel banker's algorithm for System-on-a-Chip
Jaehwan John Lee, Vincent John Mooney, III
Pages: 1304-1308
doi>10.1145/1120725.1121049
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This paper proposes a novel O(n) Parallel Banker's Algorithm (PBA) with a best-case run-time of O(1), reduced from an O(mn2) run-time complexity of the original Banker's Algorithm. We implemented the approach in hardware, which we call ...
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Hardware/software co-design using hierarchical platform-based design method
Zhihui Xiong, Sikun Li, Jihua Chen
Pages: 1309-1312
doi>10.1145/1120725.1121050
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A Hierarchical Platform-Based Design (Hi-PBD) method is put forward for SoC system design. This method divides SoC system design flow into three levels (i.e. system model level, virtual components level and real components level) to achieve separation ...
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Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip
Yan Zhang
Pages: 1313-1316
doi>10.1145/1120725.1121051
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This paper presents a statistic-based priority strategy for dynamic priority arbiters and its application was investigated for the lottery arbiter. Two set MxM registers are proposed to record the arbitration history. The period of recording arbitration ...
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Using loop invariants to fight soft errors in data caches
Sri Hari Krishna N, Seung Woo Son, Mahmut Kandemir, Feihui Li
Pages: 1317-1320
doi>10.1145/1120725.1121052
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Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicating instructions either in the spatial or temporal domain and then comparing ...
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