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Hybrid transactional memory
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Authors:
Sanjeev Kumar
Intel Labs, Santa Clara, CA
Michael Chu
University of Michigan, Ann Arbor
Christopher J. Hughes
Intel Labs, Santa Clara, CA
Partha Kundu
Intel Labs, Santa Clara, CA
Anthony Nguyen
Intel Labs, Santa Clara, CA
2006 Article
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Published in:
· Proceeding
PPoPP '06
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Pages 209 - 220
ACM
New York, NY
, USA
©2006
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ISBN:1-59593-189-9
doi>
10.1145/1122971.1123003
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Tags:
algorithms
architecture support
languages
nonblocking
parallel programming
performance
transactional memory
transactions
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