2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

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Authors: Rashed Zafar Bhatti University of Southern California, Marina del Rey, CA
Monty Denneau IBM T.J. Watson Research Center, Yorktown Heights, NY
Jeff Draper University of Southern California, Marina del Rey, CA
Published in:
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· Proceeding
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Pages 198-203
ACM New York, NY, USA ©2006
table of contents ISBN:1-59593-347-6 doi>10.1145/1127908.1127956
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology Published by ACM 2006 Article
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