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A formal approach for high level synthesis of linear analog systems
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Authors:
Soumya Pandit
Indian Institute of Technology, Kharagpur, India
Chittaranjan Mandal
Indian Institute of Technology, Kharagpur, India
Amit Patra
Indian Institute of Technology, Kharagpur, India
Published in:
· Proceeding
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Pages 345-348
ACM
New York, NY
, USA
©2006
table of contents
ISBN:1-59593-347-6
doi>
10.1145/1127908.1127987
2006 Article
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Tags:
algorithms
analog high level synthesis
architecture exploration
design
design aids
l2 sensitivity
linear systems
performance
state space model
verification
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