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Tile size selection for low-power tile-based architectures
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Authors:
John Oliver
University of California, Davis, CA
Ravishankar Rao
University of California, Davis, CA
Michael Brown
Cal Poly State University, San Luis Obispo, CA
Jennifer Mankin
Cal Poly State University, San Luis Obispo, CA
Diana Franklin
Cal Poly State University, San Luis Obispo, CA
Frederic T. Chong
University of California, Santa Barbara, CA
Venkatesh Akella
University of California, Davis, CA
2006 Article
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Published in:
· Proceeding
CF '06
Proceedings of the 3rd conference on Computing frontiers
Pages 83-94
ACM
New York, NY
, USA
©2006
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ISBN:1-59593-302-6
doi>
10.1145/1128022.1128036
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Tags:
design
media processors
multi-core processors
multiple data stream architectures
performance
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