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A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division

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Authors: David W. Matula Southern Methodist University, Dallas, TX
Lee D. McFearin Southern Methodist University, Dallas, TX
Published in:
· Proceeding
DATE '06 Proceedings of the conference on Design, automation and test in Europe: Proceedings
European Design and Automation Association 3001 Leuven, Belgium, Belgium ©2006
table of contents ISBN:3-9810801-0-6
A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division 2006 Article
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