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Physical design methodology of power gating circuits for standard-cell-based design
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Authors:
Hyung-Ock Kim
KAIST, Daejeon, Korea
Youngsoo Shin
KAIST, Daejeon, Korea
Hyuk Kim
Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea
Iksoo Eo
Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea
2006 Article
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Published in:
· Proceeding
DAC '06
Proceedings of the 43rd annual Design Automation Conference
Pages 109-112
ACM
New York, NY
, USA
©2006
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ISBN:1-59593-381-6
doi>
10.1145/1146909.1146942
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design
leakage current
low power
power gating
vlsi
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