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Building a verification test plan: trading brute force for finesse
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Authors:
J. Bergeron
Synopsys Inc.
H. Foster
Mentor Graphics
A. Piziali
Cadence Design Systems
R. S. Mitra
Texas Instruments, Inc.
C. Ahlschlager
Sun Microsystems
D. Stein
Cisco Systems, Inc.
2006 Article
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· Downloads (6 Weeks): 2
· Downloads (12 Months): 8
· Citation Count: 0
Published in:
· Proceeding
DAC '06
Proceedings of the 43rd annual Design Automation Conference
ACM
New York, NY
, USA
©2006
table of contents
ISBN:1-59593-381-6
doi>
10.1145/1146909.1147113
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Tags:
coverage
design
design verification
formal verification
functional simulation
verification
verification
verification test plan
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