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A fast SAT solver algorithm best suited to reconfigurable hardware
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Authors:
Romanelli Zuim
DCC-UFMG, Brasil
José T. de Sousa
INESC-ID Lisboa/Coreworks Lda., Portugal
Claudionor N. Coelho
DCC - UFMG, Brasil
Published in:
· Proceeding
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
ACM
New York, NY
, USA
©2006
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ISBN:1-59593-479-0
doi>
10.1145/1150343.1150380
2006 Article
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Tags:
algorithms
cnf
computer-aided design
dpll
formal verification
graph and tree search strategies
sat
verification
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