Managing bounded code caches in dynamic binary optimization systems
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REFERENCESNote: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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INDEX TERMSThe ACM Computing Classification System (CCS rev.2012)
PUBLICATION| Title | ACM Transactions on Architecture and Code Optimization (TACO) TACO Homepage table of contents archive |
| Volume 3 Issue 3, September 2006 | |
| Pages | 263-294 |
| Publication Date | 2006-09-01 (yyyy-mm-dd) |
| Publisher | ACM New York, NY, USA |
| ISSN: 1544-3566 EISSN: 1544-3973 doi>10.1145/1162690.1162692 |
REVIEWS
COMMENTSBe the first to comment To Post a comment please sign in or create a free Web account
Table of ContentsVolume 3 Issue 3, September 2006
| An approach toward profit-driven optimization | |
| Min Zhao, Bruce R. Childers, Mary Lou Soffa | |
| Pages: 231-262 | |
| doi>10.1145/1162690.1162691 | |
Full text: PDF
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Although optimizations have been applied for a number of years to improve the performance of software, problems with respect to the application of optimizations have not been adequately addressed. For example, in certain circumstances, optimizations ...
expand
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| Managing bounded code caches in dynamic binary optimization systems | |
| Kim Hazelwood, Michael D. Smith | |
| Pages: 263-294 | |
| doi>10.1145/1162690.1162692 | |
Full text: PDF
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Dynamic binary optimizers store altered copies of original program instructions in software-managed code caches in order to maximize reuse of transformed code. Code caches store code blocks that may vary in size, reference other code blocks, and carry ...
expand
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| A case for a complexity-effective, width-partitioned microarchitecture | |
| Olivier Rochecouste, Gilles Pokam, André Seznec | |
| Pages: 295-326 | |
| doi>10.1145/1162690.1162693 | |
Full text: PDF
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The analysis of program executions reveals that most integer and multimedia applications make heavy use of narrow-width operations, i.e., instructions exclusively using narrow-width operands and producing a narrow-width result. Moreover, this usage is ...
expand
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| Block-aware instruction set architecture | |
| Ahmad Zmily, Christos Kozyrakis | |
| Pages: 327-357 | |
| doi>10.1145/1162690.1162694 | |
Full text: PDF
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Instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle ...
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