A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

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Authors:	Hidehiro Fujiwara	Kobe University, Kobe, Japan
	Koji Nii	Kobe University, Kobe, Japan
	Junichi Miyakoshi	Kobe University, Kobe, Japan
	Yuichiro Murachi	Kobe University, Kobe, Japan
	Yasuhiro Morita	Kanazawa University, Ishikawa, Japan
	Hiroshi Kawaguchi	Kobe University, Kobe, Japan
	Masahiko Yoshimoto	Kobe University, Kobe, Japan

	2006 Article
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	· Proceeding
	ISLPED '06 Proceedings of the 2006 international symposium on Low power electronics and design
	Pages 61-66 ACM New York, NY, USA ©2006 table of contents ISBN:1-59593-462-6 doi>10.1145/1165573.1165589

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