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A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors
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Authors:
Pong-Fei Lu
IBM T. J. Watson Research Center, Yorktown Heights, NY
Nianzheng Cao
IBM T. J. Watson Research Center, Yorktown Heights, NY
Leon Sigal
IBM T. J. Watson Research Center, Yorktown Heights, NY
Pieter Woltgens
IBM T. J. Watson Research Center, Yorktown Heights, NY
R. Robertazzi
IBM T. J. Watson Research Center, Yorktown Heights, NY
D. Heidel
IBM T. J. Watson Research Center, Yorktown Heights, NY
2006 Article
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Published in:
· Proceeding
ISLPED '06
Proceedings of the 2006 international symposium on Low power electronics and design
Pages 85-88
ACM
New York, NY
, USA
©2006
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ISBN:1-59593-462-6
doi>
10.1145/1165573.1165593
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Tags:
design
latch
logic design
low-power
pulse latch
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