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Robust wiring networks for DfY considering timing constraints
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Authors:
Philipp V. Panitz
University of Hannover, Hannover, Germany
Markus Olbrich
University of Hannover, Hannover, Germany
Erich Barke
University of Hannover, Hannover, Germany
Jürgen Koehl
IBM Deutschland Entwicklung GmbH, Boeblingen, Germany
2007 Article
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Published in:
· Proceeding
GLSVLSI '07
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pages 43-48
ACM
New York, NY
, USA
©2007
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ISBN: 978-1-59593-605-9
doi>
10.1145/1228784.1228800
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Tags:
algorithms
design for yield
open defects
performance
placement and routing
redundant wiring
reliability
timing constraint aware
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