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Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors

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Authors: A. Robinson The University of Manchester, Manchester, United Kingdom
J. D. Garside The University of Manchester, Manchester, United Kingdom
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· Proceeding
GLSVLSI '07 Proceedings of the 17th ACM Great Lakes symposium on VLSI
ACM New York, NY, USA ©2007
table of contents ISBN: 978-1-59593-605-9 doi>10.1145/1228784.1228820
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors Published by ACM 2007 Article
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