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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology
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Authors:
Riaz Naseer
University of Southern California, Los Angeles, CA
Jeff Draper
University of Southern California, Los Angeles, CA
Younes Boulghassoul
University of Southern California, Los Angeles, CA
Sandeepan DasGupta
Vanderbilt University, Nashville, TN
Art Witulski
Vanderbilt University, Nashville, TN
2007 Article
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· Downloads (12 Months): 15
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· Proceeding
GLSVLSI '07
Proceedings of the 17th ACM Great Lakes symposium on VLSI
ACM
New York, NY
, USA
©2007
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ISBN: 978-1-59593-605-9
doi>
10.1145/1228784.1228843
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Tags:
critical charge
reliability
simulation
single event transient
soft error
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