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Structured and tuned array generation (STAG) for high-performance random logic
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Authors:
Matthew M. Ziegler
IBM T. J. Watson Research Center, Yorktown Heights, NY
Gary S. Ditlow
IBM T. J. Watson Research Center, Yorktown Heights, NY
Stephen V. Kosonocky
IBM T. J. Watson Research Center, Yorktown Heights, NY
Zhenyu (Jerry) Qi
University of Virginia, Charlottesville, VA
Mircea R. Stan
University of Virginia, Charlottesville, VA
2007 Article
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Published in:
· Proceeding
GLSVLSI '07
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pages 257-262
ACM
New York, NY
, USA
©2007
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ISBN: 978-1-59593-605-9
doi>
10.1145/1228784.1228849
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design
design automation
performance
programmable logic arrays
vlsi
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