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Modeling and estimating leakage current in series-parallel CMOS networks
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Authors:
Paulo F. Butzen
Universidade Federal do Rio Grande do Sul, Porto Algre, Brazil
Andre I. Reis
Nangate Inc, Herlev, Denmark
Chris H. Kim
University of Minnesota, Minneapolis, MN
Renato P. Ribas
Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
2007 Article
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Published in:
· Proceeding
GLSVLSI '07
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pages 269-274
ACM
New York, NY
, USA
©2007
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ISBN: 978-1-59593-605-9
doi>
10.1145/1228784.1228852
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Tags:
cmos gates
combinational logic
design
leakage current modeling
performance
performance analysis and design aids
static power dissipation
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