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Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects
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Authors:
Chittarsu Raghunandan
International Institute of Information Technology, Hyderabad, India
K. S. Sainarayanan
International Institute of Information Technology, Hyderabad, India
M. B. Srinivas
International Institute of Information Technology, Hyderabad, India
Published in:
· Proceeding
GLSVLSI '07
Proceedings of the 17th ACM Great Lakes symposium on VLSI
ACM
New York, NY
, USA
©2007
table of contents
ISBN: 978-1-59593-605-9
doi>
10.1145/1228784.1228873
2007 Article
Bibliometrics
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· Downloads (12 Months): 8
· Citation Count: 0
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advanced technologies
algorithms
algorithms implemented in hardware
bit transitions
bus-encoding scheme
crosstalk noise
decoder
delay
design
encoder
high impedance state
inductive coupling
low power
performance
simultaneous switching noise
spatial and temporal redundancy
vlsi
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