Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

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Authors: Paolo Bernardi Politecnico di Torino, Torino, Italy
Michelangelo Grosso Politecnico di Torino, Torino, Italy
Matteo Sonza Reorda Politecnico di Torino, Torino, Italy
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· Proceeding
GLSVLSI '07 Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pages 411-416
ACM New York, NY, USA ©2007
table of contents ISBN: 978-1-59593-605-9 doi>10.1145/1228784.1228881
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems Published by ACM 2007 Article
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