Latency hiding through multithreading on a network processor

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Authors: Xiaofeng Guo Intel Asia-Pacific Research & Development Ltd., Shanghai, China
Jinquan Dai Intel Asia-Pacific Research & Development Ltd., Shanghai, China
Long Li Intel Asia-Pacific Research & Development Ltd., Shanghai, China
Zhiyuan Lv Intel Asia-Pacific Research & Development Ltd., Shanghai, China
Prashant R. Chandra Intel Corporation, Santa Clara, CA
Latency hiding through multithreading on a network processor Published by ACM 2007 Article
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· Proceeding
PPoPP '07 Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Pages 130 - 131
ACM New York, NY, USA ©2007
table of contents ISBN: 978-1-59593-602-8 doi>10.1145/1229428.1229451

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