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Parallel circuit simulation using hierarchical relaxation
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Authors:
G. G. Hung
Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
Y. C. Wen
Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
K. Gallivan
Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
R. Saleh
Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
1991 Article
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Published in:
· Proceeding
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Pages 394-399
ACM
New York, NY
, USA
©1990
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ISBN:0-89791-363-9
doi>
10.1145/123186.123316
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algorithms
parallel circuits
performance
simulation
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