SIGN IN
SIGN UP
Designing application-specific networks on chips with floorplan information
Full Text:
PDF
Buy this Article
Authors:
Srinivasan Murali
Stanford University, Stanford
Paolo Meloni
University of Cagliari, Cagliari, Italy
Federico Angiolini
University of Bologna, Bologna, Italy
David Atienza
LSI, EPFL, Lausanne, Switzerland and Complutense University of Madrid (UCM), Madrid, Spain
Salvatore Carta
University of Cagliari, Cagliari, Italy
Luca Benini
University of Bologna, Bologna, Italy
Giovanni De Micheli
University of Bologna, Bologna, Italy
Luigi Raffo
University of Cagliari, Cagliari, Italy
2006 Article
Bibliometrics
· Downloads (6 Weeks): 6
· Downloads (12 Months): 46
· Downloads (cumulative): 604
· Citation Count: 49
Published in:
· Proceeding
ICCAD '06
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Pages 355-362
ACM
New York, NY
, USA
©2006
table of contents
ISBN:1-59593-389-1
doi>
10.1145/1233501.1233573
Tools and Resources
Buy this Article
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
ICCAD'13
Share:
|
Tags:
deadlock-free routing
design
design management
floorplan
layout
networks on chips
performance
placement and routing
topology
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder