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Selective code transformation for dual instruction set processors
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Authors:
Sheayun Lee
Samsung Electronics, Hwasung City, Gyeonggi-Do, Korea
Jaejin Lee
Seoul National University, Seoul, Korea
Chang Yun Park
Chungang University, Seoul, Korea
Sang Lyul Min
Seoul National University, Seoul, Korea
2007 Article
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ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
TECS Homepage
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Volume 6 Issue 2, May 2007
Article No. 10
ACM
New York, NY
, USA
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doi>
10.1145/1234675.1234677
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Tags:
code generation
design
dual instruction set processors
general
mixed-width instruction set architecture
optimization
performance
reduced bid-width instruction set architecture
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