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An effective on-chip preloading scheme to reduce data access penalty
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Authors:
Jean-Loup Baer
Department of Computer Science and Engineering, University of Washington, Seattle, WA
Tien-Fu Chen
Department of Computer Science and Engineering, University of Washington, Seattle, WA
Published in:
· Proceeding
Supercomputing '91 Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Pages 176-186
ACM
New York, NY
, USA
©1991
table of contents
ISBN:0-89791-459-7
doi>
10.1145/125826.125932
1991 Article
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algorithms
cache memories
design
interleaved memories
performance
simulation
super computers
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