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Design fault directed test generation for microprocessor validation

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Authors: Deepak A. Mathaikutty FERMAT Lab, Virginia Tech Blacksburg, VA
Sandeep K. Shukla FERMAT Lab, Virginia Tech Blacksburg, VA
Sreekumar V. Kodakara The University of Minnesota, Minneapolis, MN
David Lilja The University of Minnesota, Minneapolis, MN
Ajit Dingankar Validation Tools, Intel Corporation, Folsom, CA
Design fault directed test generation for microprocessor validation 2007 Article
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DATE '07 Proceedings of the conference on Design, automation and test in Europe
EDA Consortium San Jose, CA, USA ©2007
table of contents ISBN: 978-3-9810801-2-4

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