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Silicon speedpath measurement and feedback into EDA flows
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Authors:
Kip Killpack
Intel Strategic CAD Labs, Hillsboro, OR
Chandramouli Kashyap
Intel Strategic CAD Labs, Hillsboro, OR
Eli Chiprout
Intel Strategic CAD Labs, Hillsboro, OR
Published in:
· Proceeding
DAC '07
Proceedings of the 44th annual Design Automation Conference
ACM
New York, NY
, USA
©2007
table of contents
ISBN: 978-1-59593-627-1
doi>
10.1145/1278480.1278581
2007 Article
Bibliometrics
· Downloads (6 Weeks): 3
· Downloads (12 Months): 30
· Citation Count: 13
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DAC '12
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Tags:
correlation
design
design aids
measurement
measurement
performance
performance analysis and design aids
reliability, testing, and fault-tolerance
silicon
speedpath
timing
verification
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