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Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture
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Authors:
Florian Dittmann
University Paderborn/HNI, Paderborn, Germany
Achim Rettberg
University Paderborn/C-LAB, Paderborn, Germany
Raphael Weber
University Paderborn/C-LAB, Paderborn, Germany
Published in:
· Proceeding
SBCCI '07
Proceedings of the 20th annual conference on Integrated circuits and systems design
Pages 153-158
ACM
New York, NY
, USA
©2007
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ISBN: 978-1-59593-816-9
doi>
10.1145/1284480.1284526
2007 Article
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SBCCI '13
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Tags:
algorithms
bit-serial architecture
design
high-level synthesis
optimization
performance analysis and design aids
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