Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

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Authors: Lei Cheng Univ. of Illinois at UC, Champaign, IL
Deming Chen Univ. of Illinois at UC, Champaign, IL
Martin D. F. Wong Univ. of Illinois at UC, Champaign, IL
Mike Hutton Altera Corp., San Jose, CA
Jason Govig Altera Corp., San Jose, CA
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains 2007 Article
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· Proceeding
ICCAD '07 Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pages 370-375
IEEE Press Piscataway, NJ, USA ©2007
table of contents ISBN:1-4244-1382-6

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