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An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
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Authors:
Haakon Dybdahl
Norwegian University of Science and Technology, Trondheim, Norway
Per Stenström
Chalmers University of Technology, Goteborg, Sweden
Lasse Natvig
Norwegian University of Science and Technology, Trondheim, Norway
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· Newsletter
ACM SIGARCH Computer Architecture News
archive
Volume 35 Issue 4, September 2007
ACM
New York, NY
, USA
table of contents
doi>
10.1145/1327312.1327320
2007 Article
Column
Bibliometrics
· Downloads (6 Weeks): 2
· Downloads (12 Months): 59
· Citation Count: 2
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algorithms
cache memories
experimentation
performance
performance attributes
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